diff mbox series

[v4,130/163] target/sh4: Use tcg_gen_addcio_i32 for addc

Message ID 20250415192515.232910-131-richard.henderson@linaro.org (mailing list archive)
State New
Headers show
Series tcg: Convert to TCGOutOp structures | expand

Commit Message

Richard Henderson April 15, 2025, 7:24 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/translate.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

Comments

Pierrick Bouvier April 16, 2025, 7:09 p.m. UTC | #1 
On 4/15/25 12:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/sh4/translate.c | 10 ++--------
>   1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 2ef48b1d17..e8029c0c7a 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -694,14 +694,8 @@ static void _decode_opc(DisasContext * ctx)
>           tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
>           return;
>       case 0x300e: /* addc Rm,Rn */
> -        {
> -            TCGv t0, t1;
> -            t0 = tcg_constant_tl(0);
> -            t1 = tcg_temp_new();
> -            tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
> -            tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
> -                             REG(B11_8), t0, t1, cpu_sr_t);
> -        }
> +        tcg_gen_addcio_i32(REG(B11_8), cpu_sr_t,
> +                           REG(B11_8), REG(B7_4), cpu_sr_t);
>           return;
>       case 0x300f: /* addv Rm,Rn */
>           {

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 2ef48b1d17..e8029c0c7a 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -694,14 +694,8 @@  static void _decode_opc(DisasContext * ctx)
         tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
         return;
     case 0x300e: /* addc Rm,Rn */
-        {
-            TCGv t0, t1;
-            t0 = tcg_constant_tl(0);
-            t1 = tcg_temp_new();
-            tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
-            tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
-                             REG(B11_8), t0, t1, cpu_sr_t);
-        }
+        tcg_gen_addcio_i32(REG(B11_8), cpu_sr_t,
+                           REG(B11_8), REG(B7_4), cpu_sr_t);
         return;
     case 0x300f: /* addv Rm,Rn */
         {