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Lunev\" via" X-Patchwork-Id: 10575899 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25E171579 for ; Fri, 24 Aug 2018 20:51:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17F472CCFE for ; Fri, 24 Aug 2018 20:51:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0C56A2CCF4; Fri, 24 Aug 2018 20:51:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 95A092CCCE for ; Fri, 24 Aug 2018 20:51:21 +0000 (UTC) Received: from localhost ([::1]:43601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftJ3A-0003N7-Pe for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 Aug 2018 16:51:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41387) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftI0r-0006Ww-LH for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:44:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ftI0m-0003xH-Ig for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:44:53 -0400 Received: from smtp-fw-2101.amazon.com ([72.21.196.25]:59543) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ftI0l-0003vd-0W for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:44:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535139885; x=1566675885; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=326HZq1/zPO2XKUvWdTno1jzcAdmb518/u++N+zFzhQ=; b=MHFhaWzFprHh/isChRyVOflA4IDhJD32JlkTW/0uny8EJW+oa5fUnX3Y kkKfh3B5JViAxTz4oy28su5TUezNCWgondqTodtyVMKEqUPK8KDk+d3kK pD83w/imVfQ43auJ1m8B4ABlowVemJ8yBtt9py4QbZWTRG0axpi4h9DlR 4=; X-IronPort-AV: E=Sophos;i="5.53,283,1531785600"; d="scan'208";a="694273973" Received: from iad6-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-2c-1968f9fa.us-west-2.amazon.com) ([10.124.125.2]) by smtp-border-fw-out-2101.iad2.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 24 Aug 2018 19:44:44 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2c-1968f9fa.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7OJigcs130162 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 24 Aug 2018 19:44:43 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7OJigI0020014; Fri, 24 Aug 2018 15:44:42 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7OJig0i020013; Fri, 24 Aug 2018 15:44:42 -0400 To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 15:44:05 -0400 Message-Id: <20819a8ef4216527bccc346de4a50ce14386034c.1535133089.git.jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: References: Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.196.25 X-Mailman-Approved-At: Fri, 24 Aug 2018 16:47:11 -0400 Subject: [Qemu-devel] [PATCH 4/7] target/mips: Add MXU instruction D16MUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Craig Janeczek via Qemu-devel From: "Denis V. Lunev\" via" Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adds support for emulating the D16MUL instruction. Signed-off-by: Craig Janeczek --- target/mips/translate.c | 55 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4ccccd5849..64fc6089bb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -365,6 +365,7 @@ enum { OPC_DCLZ = 0x24 | OPC_SPECIAL2, OPC_DCLO = 0x25 | OPC_SPECIAL2, /* MXU */ + OPC_MXU_D16MUL = 0x08 | OPC_SPECIAL2, OPC_MXU_S8LDD = 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2, @@ -3794,15 +3795,28 @@ typedef union { uint32_t rb:5; uint32_t special2:6; } S8LDD; + + struct { + uint32_t op:6; + uint32_t xra:4; + uint32_t xrb:4; + uint32_t xrc:4; + uint32_t xrd:4; + uint32_t optn2:2; + uint32_t sel:2; + uint32_t special2:6; + } D16MUL; } MXU_OPCODE; /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { #ifndef TARGET_MIPS64 /* Only works in 32 bit mode */ - TCGv t0, t1; + TCGv t0, t1, t2, t3; t0 = tcg_temp_new(); t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); MXU_OPCODE *opcode = (MXU_OPCODE *)&ctx->opcode; switch (opc) { @@ -3882,10 +3896,48 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) } gen_store_mxu_gpr(t0, opcode->S8LDD.xra); break; + + case OPC_MXU_D16MUL: + if (opcode->D16MUL.sel == 1) { + /* D16MULE is not supported */ + generate_exception_end(ctx, EXCP_RI); + } + gen_load_mxu_gpr(t1, opcode->D16MUL.xrb); + tcg_gen_ext16s_tl(t0, t1); + tcg_gen_shri_tl(t1, t1, 16); + tcg_gen_ext16s_tl(t1, t1); + gen_load_mxu_gpr(t3, opcode->D16MUL.xrc); + tcg_gen_ext16s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 16); + tcg_gen_ext16s_tl(t3, t3); + + switch (opcode->D16MUL.optn2) { + case 0: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, opcode->D16MUL.xra); + gen_store_mxu_gpr(t2, opcode->D16MUL.xrd); + break; } tcg_temp_free(t0); tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); #else generate_exception_end(ctx, EXCP_RI); #endif @@ -17975,6 +18027,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32I2M: case OPC_MXU_S32M2I: case OPC_MXU_S8LDD: + case OPC_MXU_D16MUL: gen_mxu(ctx, op1); break;