From patchwork Wed Aug 2 09:59:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 9876501 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 409C86037D for ; Wed, 2 Aug 2017 10:00:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1988A2879B for ; Wed, 2 Aug 2017 10:00:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0E41A287A2; Wed, 2 Aug 2017 10:00:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D9B32879B for ; Wed, 2 Aug 2017 10:00:55 +0000 (UTC) Received: from localhost ([::1]:46511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcqSR-0003L2-Ik for patchwork-qemu-devel@patchwork.kernel.org; Wed, 02 Aug 2017 06:00:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcqRD-0003JQ-Ns for qemu-devel@nongnu.org; Wed, 02 Aug 2017 05:59:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcqRC-0002cG-4N for qemu-devel@nongnu.org; Wed, 02 Aug 2017 05:59:35 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23078) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcqRB-0002aN-Uf for qemu-devel@nongnu.org; Wed, 02 Aug 2017 05:59:34 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 03EE45F07D05; Wed, 2 Aug 2017 10:59:28 +0100 (IST) Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Wed, 2 Aug 2017 10:59:30 +0100 From: James Hogan To: Date: Wed, 2 Aug 2017 10:59:17 +0100 Message-ID: <248e7141b59e3cce8768f8210ade7f19108c92fa.1501667615.git-series.james.hogan@imgtec.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH for-2.10 3/3] target/mips: Fix RDHWR CC with icount X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , James Hogan , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled it must set can_do_io while it calls the helper to avoid the "Bad icount read" error. It should also break out of the translation loop to ensure that timer interrupts are immediately handled. Fixes: 2e70f6efa8b9 ("Add instruction counter.") Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Yongbok Kim Reviewed-by: Richard Henderson --- I've based this on MFC0 Count, but this instruction is also available to usermode (e.g. CONFIG_USER_ONLY), which I presume is still fine. --- target/mips/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+), 0 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6e724ac71dcd..f29092f6d4ac 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10759,8 +10759,19 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_store_gpr(t0, rt); break; case 2: + if (ctx->tb->cflags & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_rdhwr_cc(t0, cpu_env); + if (ctx->tb->cflags & CF_USE_ICOUNT) { + gen_io_end(); + } gen_store_gpr(t0, rt); + /* Break the TB to be able to take timer interrupts immediately + after reading count. BS_STOP isn't sufficient, we need to ensure + we break completely out of translated code. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; break; case 3: gen_helper_rdhwr_ccres(t0, cpu_env);