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Lunev\" via" X-Patchwork-Id: 10575889 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E183174C for ; Fri, 24 Aug 2018 20:48:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4EA712CC7A for ; Fri, 24 Aug 2018 20:48:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3EF5A2CC94; Fri, 24 Aug 2018 20:48:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B02DD2CC7A for ; Fri, 24 Aug 2018 20:48:28 +0000 (UTC) Received: from localhost ([::1]:43581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftJ0N-0000eX-N4 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 Aug 2018 16:48:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41343) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftI0o-0006Lf-Um for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:44:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ftI0k-0003vk-Sh for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:44:50 -0400 Received: from smtp-fw-4101.amazon.com ([72.21.198.25]:1250) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ftI0k-0003td-MM for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:44:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535139886; x=1566675886; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=l8lvo731UE1DnZFe6ac++elDcN+NjgyJh4da38bI5Fo=; b=v5o1lUmpmIzcWDXYQNVNKWJ0FmVzQmho6vZkCkdEFLf0EyOmUIYu/A0u X8vcED19SuNoUqDFm1595Ys8/m4dK3WBnmG4BxcOQNnlxosg6bTFlPfdc fC3n/iWEoH4PpLvYKOZVHsH3ewBXljxbA747clRRxPkggdUUfEqhjG0Cv I=; X-IronPort-AV: E=Sophos;i="5.53,283,1531785600"; d="scan'208";a="735310296" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2b-859fe132.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-4101.iad4.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 24 Aug 2018 19:44:45 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2b-859fe132.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7OJigSj096107 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 24 Aug 2018 19:44:43 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7OJigSj020023; Fri, 24 Aug 2018 15:44:42 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7OJigut020022; Fri, 24 Aug 2018 15:44:42 -0400 To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 15:44:07 -0400 Message-Id: <38ffde3b6d6eed8b8f302298474dfa992fd752a1.1535133089.git.jancraig@amazon.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: References: Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 72.21.198.25 X-Mailman-Approved-At: Fri, 24 Aug 2018 16:47:11 -0400 Subject: [Qemu-devel] [PATCH 6/7] target/mips: Add MXU instructions Q8MUL and Q8MULSU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Craig Janeczek via Qemu-devel From: "Denis V. Lunev\" via" Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adds support for emulating the Q8MUL and Q8MULSU instructions. Signed-off-by: Craig Janeczek --- target/mips/translate.c | 75 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 221076711d..ae6cfc3d7c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -370,6 +370,7 @@ enum { OPC_MXU_S8LDD = 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2, + OPC_MXU_Q8MUL = 0x38 | OPC_SPECIAL2, /* Special */ OPC_SDBBP = 0x3F | OPC_SPECIAL2, }; @@ -3818,17 +3819,32 @@ typedef union { uint32_t aptn2:2; uint32_t special2:6; } D16MAC; + + struct { + uint32_t op:6; + uint32_t xra:4; + uint32_t xrb:4; + uint32_t xrc:4; + uint32_t xrd:4; + uint32_t sel:2; + uint32_t:2; + uint32_t special2:6; + } Q8MUL; } MXU_OPCODE; /* MXU Instructions */ static void gen_mxu(DisasContext *ctx, uint32_t opc) { #ifndef TARGET_MIPS64 /* Only works in 32 bit mode */ - TCGv t0, t1, t2, t3; + TCGv t0, t1, t2, t3, t4, t5, t6, t7; t0 = tcg_temp_new(); t1 = tcg_temp_new(); t2 = tcg_temp_new(); t3 = tcg_temp_new(); + t4 = tcg_temp_new(); + t5 = tcg_temp_new(); + t6 = tcg_temp_new(); + t7 = tcg_temp_new(); MXU_OPCODE *opcode = (MXU_OPCODE *)&ctx->opcode; switch (opc) { @@ -3997,12 +4013,68 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_store_mxu_gpr(t3, opcode->D16MAC.xra); gen_store_mxu_gpr(t2, opcode->D16MAC.xrd); break; + + case OPC_MXU_Q8MUL: + gen_load_mxu_gpr(t3, opcode->Q8MUL.xrb); + gen_load_mxu_gpr(t7, opcode->Q8MUL.xrc); + + if (opcode->Q8MUL.sel == 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, opcode->Q8MUL.xrd); + gen_store_mxu_gpr(t1, opcode->Q8MUL.xra); + break; } tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); #else generate_exception_end(ctx, EXCP_RI); #endif @@ -18094,6 +18166,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S8LDD: case OPC_MXU_D16MUL: case OPC_MXU_D16MAC: + case OPC_MXU_Q8MUL: gen_mxu(ctx, op1); break;