diff mbox series

[v4,25/33] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate()

Message ID 49e2b7e5a0fb98fd3f8a6d3c0c8ac2a05ebceb7a.1715209155.git.balaton@eik.bme.hu (mailing list archive)
State New, archived
Headers show
Series Misc PPC exception and BookE MMU clean ups | expand

Commit Message

BALATON Zoltan May 8, 2024, 11:36 p.m. UTC 
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
reduce ppc_jumbo_xlate() further.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 target/ppc/mmu_common.c | 148 ++++++++++++++++++++++++++--------------
 1 file changed, 98 insertions(+), 50 deletions(-)

Comments

Nicholas Piggin May 9, 2024, 6:17 a.m. UTC | #1 
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
>

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>  target/ppc/mmu_common.c | 148 ++++++++++++++++++++++++++--------------
>  1 file changed, 98 insertions(+), 50 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 53ffcc795d..be0565f19c 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1089,21 +1089,9 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>                                       MMUAccessType access_type, int type,
>                                       int mmu_idx)
>  {
> -    bool real_mode;
> -
> -    if (env->mmu_model == POWERPC_MMU_BOOKE) {
> -        return mmubooke_get_physical_address(env, &ctx->raddr, &ctx->prot,
> -                                             eaddr, access_type);
> -    } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> -        return mmubooke206_get_physical_address(env, &ctx->raddr, &ctx->prot,
> -                                                eaddr, access_type, mmu_idx);
> -    }
> -
> -    real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> -                                      : !FIELD_EX64(env->msr, MSR, DR);
> -    if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
> -                      env->mmu_model == POWERPC_MMU_SOFT_4xx ||
> -                      env->mmu_model == POWERPC_MMU_REAL)) {
> +    bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
> +                                           : !FIELD_EX64(env->msr, MSR, DR);
> +    if (real_mode) {
>          ctx->raddr = eaddr;
>          ctx->prot = PAGE_RWX;
>          return 0;
> @@ -1113,6 +1101,8 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
>      case POWERPC_MMU_SOFT_6xx:
>          return mmu6xx_get_physical_address(env, ctx, eaddr, access_type, type);
>      case POWERPC_MMU_SOFT_4xx:
> +        /* avoid maybe used uninitialized warnings for unused fields in ctx */
> +        memset(ctx, 0, sizeof(*ctx));
>          return mmu40x_get_physical_address(env, &ctx->raddr, &ctx->prot, eaddr,
>                                             access_type);
>      case POWERPC_MMU_REAL:
> @@ -1177,6 +1167,93 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
>      env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
>  }
>  
> +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
> +                            MMUAccessType access_type,
> +                            hwaddr *raddrp, int *psizep, int *protp,
> +                            int mmu_idx, bool guest_visible)
> +{
> +    CPUState *cs = CPU(cpu);
> +    CPUPPCState *env = &cpu->env;
> +    hwaddr raddr;
> +    int prot, ret;
> +
> +    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> +        ret = mmubooke206_get_physical_address(env, &raddr, &prot, eaddr,
> +                                               access_type, mmu_idx);
> +    } else {
> +        ret = mmubooke_get_physical_address(env, &raddr, &prot, eaddr,
> +                                            access_type);
> +    }
> +    if (ret == 0) {
> +        *raddrp = raddr;
> +        *protp = prot;
> +        *psizep = TARGET_PAGE_BITS;
> +        return true;
> +    } else if (!guest_visible) {
> +        return false;
> +    }
> +
> +    log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> +    if (access_type == MMU_INST_FETCH) {
> +        switch (ret) {
> +        case -1:
> +            /* No matches in page tables or TLB */
> +            switch (env->mmu_model) {
> +            case POWERPC_MMU_BOOKE206:
> +                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> +                /* fall through */
> +            case POWERPC_MMU_BOOKE:
> +                cs->exception_index = POWERPC_EXCP_ITLB;
> +                env->error_code = 0;
> +                env->spr[SPR_BOOKE_DEAR] = eaddr;
> +                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> +                break;
> +            default:
> +                g_assert_not_reached();
> +            }
> +            break;
> +        case -2:
> +            /* Access rights violation */
> +            cs->exception_index = POWERPC_EXCP_ISI;
> +            env->error_code = 0;
> +            break;
> +        case -3:
> +            /* No execute protection violation */
> +            cs->exception_index = POWERPC_EXCP_ISI;
> +            env->spr[SPR_BOOKE_ESR] = 0;
> +            env->error_code = 0;
> +            break;
> +        }
> +    } else {
> +        switch (ret) {
> +        case -1:
> +            /* No matches in page tables or TLB */
> +            switch (env->mmu_model) {
> +            case POWERPC_MMU_BOOKE206:
> +                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> +                /* fall through */
> +            case POWERPC_MMU_BOOKE:
> +                cs->exception_index = POWERPC_EXCP_DTLB;
> +                env->error_code = 0;
> +                env->spr[SPR_BOOKE_DEAR] = eaddr;
> +                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> +                break;
> +            default:
> +                g_assert_not_reached();
> +            }
> +            break;
> +        case -2:
> +            /* Access rights violation */
> +            cs->exception_index = POWERPC_EXCP_DSI;
> +            env->error_code = 0;
> +            env->spr[SPR_BOOKE_DEAR] = eaddr;
> +            env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> +            break;
> +        }
> +    }
> +    return false;
> +}
> +
>  /* Perform address translation */
>  /* TODO: Split this by mmu_model. */
>  static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> @@ -1229,15 +1306,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
>                  env->spr[SPR_40x_DEAR] = eaddr;
>                  env->spr[SPR_40x_ESR] = 0x00000000;
>                  break;
> -            case POWERPC_MMU_BOOKE206:
> -                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> -                /* fall through */
> -            case POWERPC_MMU_BOOKE:
> -                cs->exception_index = POWERPC_EXCP_ITLB;
> -                env->error_code = 0;
> -                env->spr[SPR_BOOKE_DEAR] = eaddr;
> -                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> -                break;
>              case POWERPC_MMU_REAL:
>                  cpu_abort(cs, "PowerPC in real mode should never raise "
>                                "any MMU exceptions\n");
> @@ -1248,23 +1316,12 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
>          case -2:
>              /* Access rights violation */
>              cs->exception_index = POWERPC_EXCP_ISI;
> -            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                env->error_code = 0;
> -            } else {
> -                env->error_code = 0x08000000;
> -            }
> +            env->error_code = 0x08000000;
>              break;
>          case -3:
>              /* No execute protection violation */
> -            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                env->spr[SPR_BOOKE_ESR] = 0x00000000;
> -                env->error_code = 0;
> -            } else {
> -                env->error_code = 0x10000000;
> -            }
>              cs->exception_index = POWERPC_EXCP_ISI;
> +            env->error_code = 0x10000000;
>              break;
>          case -4:
>              /* Direct store exception */
> @@ -1305,15 +1362,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
>                      env->spr[SPR_40x_ESR] = 0x00000000;
>                  }
>                  break;
> -            case POWERPC_MMU_BOOKE206:
> -                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> -                /* fall through */
> -            case POWERPC_MMU_BOOKE:
> -                cs->exception_index = POWERPC_EXCP_DTLB;
> -                env->error_code = 0;
> -                env->spr[SPR_BOOKE_DEAR] = eaddr;
> -                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> -                break;
>              case POWERPC_MMU_REAL:
>                  cpu_abort(cs, "PowerPC in real mode should never raise "
>                                "any MMU exceptions\n");
> @@ -1330,10 +1378,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
>                  if (access_type == MMU_DATA_STORE) {
>                      env->spr[SPR_40x_ESR] |= 0x00800000;
>                  }
> -            } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> -                       (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> -                env->spr[SPR_BOOKE_DEAR] = eaddr;
> -                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
>              } else {
>                  env->spr[SPR_DAR] = eaddr;
>                  if (access_type == MMU_DATA_STORE) {
> @@ -1412,6 +1456,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
>      case POWERPC_MMU_32B:
>          return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
>                                 psizep, protp, mmu_idx, guest_visible);
> +    case POWERPC_MMU_BOOKE:
> +    case POWERPC_MMU_BOOKE206:
> +        return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
> +                               psizep, protp, mmu_idx, guest_visible);
>      case POWERPC_MMU_MPC8xx:
>          cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implemented\n");
>      default:
diff mbox series

Patch

diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 53ffcc795d..be0565f19c 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1089,21 +1089,9 @@  static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
                                      MMUAccessType access_type, int type,
                                      int mmu_idx)
 {
-    bool real_mode;
-
-    if (env->mmu_model == POWERPC_MMU_BOOKE) {
-        return mmubooke_get_physical_address(env, &ctx->raddr, &ctx->prot,
-                                             eaddr, access_type);
-    } else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
-        return mmubooke206_get_physical_address(env, &ctx->raddr, &ctx->prot,
-                                                eaddr, access_type, mmu_idx);
-    }
-
-    real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
-                                      : !FIELD_EX64(env->msr, MSR, DR);
-    if (real_mode && (env->mmu_model == POWERPC_MMU_SOFT_6xx ||
-                      env->mmu_model == POWERPC_MMU_SOFT_4xx ||
-                      env->mmu_model == POWERPC_MMU_REAL)) {
+    bool real_mode = (type == ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, IR)
+                                           : !FIELD_EX64(env->msr, MSR, DR);
+    if (real_mode) {
         ctx->raddr = eaddr;
         ctx->prot = PAGE_RWX;
         return 0;
@@ -1113,6 +1101,8 @@  static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
     case POWERPC_MMU_SOFT_6xx:
         return mmu6xx_get_physical_address(env, ctx, eaddr, access_type, type);
     case POWERPC_MMU_SOFT_4xx:
+        /* avoid maybe used uninitialized warnings for unused fields in ctx */
+        memset(ctx, 0, sizeof(*ctx));
         return mmu40x_get_physical_address(env, &ctx->raddr, &ctx->prot, eaddr,
                                            access_type);
     case POWERPC_MMU_REAL:
@@ -1177,6 +1167,93 @@  static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
     env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
 }
 
+static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
+                            MMUAccessType access_type,
+                            hwaddr *raddrp, int *psizep, int *protp,
+                            int mmu_idx, bool guest_visible)
+{
+    CPUState *cs = CPU(cpu);
+    CPUPPCState *env = &cpu->env;
+    hwaddr raddr;
+    int prot, ret;
+
+    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
+        ret = mmubooke206_get_physical_address(env, &raddr, &prot, eaddr,
+                                               access_type, mmu_idx);
+    } else {
+        ret = mmubooke_get_physical_address(env, &raddr, &prot, eaddr,
+                                            access_type);
+    }
+    if (ret == 0) {
+        *raddrp = raddr;
+        *protp = prot;
+        *psizep = TARGET_PAGE_BITS;
+        return true;
+    } else if (!guest_visible) {
+        return false;
+    }
+
+    log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
+    if (access_type == MMU_INST_FETCH) {
+        switch (ret) {
+        case -1:
+            /* No matches in page tables or TLB */
+            switch (env->mmu_model) {
+            case POWERPC_MMU_BOOKE206:
+                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+                /* fall through */
+            case POWERPC_MMU_BOOKE:
+                cs->exception_index = POWERPC_EXCP_ITLB;
+                env->error_code = 0;
+                env->spr[SPR_BOOKE_DEAR] = eaddr;
+                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+            break;
+        case -2:
+            /* Access rights violation */
+            cs->exception_index = POWERPC_EXCP_ISI;
+            env->error_code = 0;
+            break;
+        case -3:
+            /* No execute protection violation */
+            cs->exception_index = POWERPC_EXCP_ISI;
+            env->spr[SPR_BOOKE_ESR] = 0;
+            env->error_code = 0;
+            break;
+        }
+    } else {
+        switch (ret) {
+        case -1:
+            /* No matches in page tables or TLB */
+            switch (env->mmu_model) {
+            case POWERPC_MMU_BOOKE206:
+                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
+                /* fall through */
+            case POWERPC_MMU_BOOKE:
+                cs->exception_index = POWERPC_EXCP_DTLB;
+                env->error_code = 0;
+                env->spr[SPR_BOOKE_DEAR] = eaddr;
+                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+                break;
+            default:
+                g_assert_not_reached();
+            }
+            break;
+        case -2:
+            /* Access rights violation */
+            cs->exception_index = POWERPC_EXCP_DSI;
+            env->error_code = 0;
+            env->spr[SPR_BOOKE_DEAR] = eaddr;
+            env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
+            break;
+        }
+    }
+    return false;
+}
+
 /* Perform address translation */
 /* TODO: Split this by mmu_model. */
 static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
@@ -1229,15 +1306,6 @@  static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
                 env->spr[SPR_40x_DEAR] = eaddr;
                 env->spr[SPR_40x_ESR] = 0x00000000;
                 break;
-            case POWERPC_MMU_BOOKE206:
-                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
-                /* fall through */
-            case POWERPC_MMU_BOOKE:
-                cs->exception_index = POWERPC_EXCP_ITLB;
-                env->error_code = 0;
-                env->spr[SPR_BOOKE_DEAR] = eaddr;
-                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
-                break;
             case POWERPC_MMU_REAL:
                 cpu_abort(cs, "PowerPC in real mode should never raise "
                               "any MMU exceptions\n");
@@ -1248,23 +1316,12 @@  static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
         case -2:
             /* Access rights violation */
             cs->exception_index = POWERPC_EXCP_ISI;
-            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                env->error_code = 0;
-            } else {
-                env->error_code = 0x08000000;
-            }
+            env->error_code = 0x08000000;
             break;
         case -3:
             /* No execute protection violation */
-            if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                env->spr[SPR_BOOKE_ESR] = 0x00000000;
-                env->error_code = 0;
-            } else {
-                env->error_code = 0x10000000;
-            }
             cs->exception_index = POWERPC_EXCP_ISI;
+            env->error_code = 0x10000000;
             break;
         case -4:
             /* Direct store exception */
@@ -1305,15 +1362,6 @@  static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
                     env->spr[SPR_40x_ESR] = 0x00000000;
                 }
                 break;
-            case POWERPC_MMU_BOOKE206:
-                booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
-                /* fall through */
-            case POWERPC_MMU_BOOKE:
-                cs->exception_index = POWERPC_EXCP_DTLB;
-                env->error_code = 0;
-                env->spr[SPR_BOOKE_DEAR] = eaddr;
-                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
-                break;
             case POWERPC_MMU_REAL:
                 cpu_abort(cs, "PowerPC in real mode should never raise "
                               "any MMU exceptions\n");
@@ -1330,10 +1378,6 @@  static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
                 if (access_type == MMU_DATA_STORE) {
                     env->spr[SPR_40x_ESR] |= 0x00800000;
                 }
-            } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
-                       (env->mmu_model == POWERPC_MMU_BOOKE206)) {
-                env->spr[SPR_BOOKE_DEAR] = eaddr;
-                env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
             } else {
                 env->spr[SPR_DAR] = eaddr;
                 if (access_type == MMU_DATA_STORE) {
@@ -1412,6 +1456,10 @@  bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
     case POWERPC_MMU_32B:
         return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
                                psizep, protp, mmu_idx, guest_visible);
+    case POWERPC_MMU_BOOKE:
+    case POWERPC_MMU_BOOKE206:
+        return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
+                               psizep, protp, mmu_idx, guest_visible);
     case POWERPC_MMU_MPC8xx:
         cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implemented\n");
     default: