From patchwork Sat Feb 25 18:31:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 9604301 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C408960414 for ; Sat, 4 Mar 2017 22:45:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B60FC28343 for ; Sat, 4 Mar 2017 22:45:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AAF1C283B3; Sat, 4 Mar 2017 22:45:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=2.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4EFF128343 for ; Sat, 4 Mar 2017 22:45:48 +0000 (UTC) Received: from localhost ([::1]:36816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ckIQt-0005O9-C9 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 04 Mar 2017 17:45:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ckIO1-0003HR-6J for qemu-devel@nongnu.org; Sat, 04 Mar 2017 17:42:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ckINy-0000sb-6X for qemu-devel@nongnu.org; Sat, 04 Mar 2017 17:42:49 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:26744) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ckINx-0000pp-R9; Sat, 04 Mar 2017 17:42:46 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 492F5745972; Sat, 4 Mar 2017 23:42:38 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id C58E37456D4; Sat, 4 Mar 2017 23:42:37 +0100 (CET) Message-Id: <4bd61f7ecdba6f205e30f0b712c65036951f1375.1488665935.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Sat, 25 Feb 2017 19:31:24 +0100 To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v4 06/13] sm501: Add emulation of chip connected via PCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Magnus Damm , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Only the display controller part is created automatically on PCI Signed-off-by: BALATON Zoltan Reviewed-by: Peter Maydell --- v2: Split off removing dependency on base address to separate patch v3: Added reset function and PCI ID constant definitions in pci_ids.h v4: Return error for invalid VRAM size, set bit in misc_control for PCI bus hw/display/sm501.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/pci/pci_ids.h | 3 +++ 2 files changed, 68 insertions(+) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 09c023d..c92a5fa 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -32,6 +32,7 @@ #include "ui/console.h" #include "hw/devices.h" #include "hw/sysbus.h" +#include "hw/pci/pci.h" #include "qemu/range.h" #include "ui/pixel_ops.h" #include "exec/address-spaces.h" @@ -1547,9 +1548,73 @@ static const TypeInfo sm501_sysbus_info = { .class_init = sm501_sysbus_class_init, }; +#define TYPE_PCI_SM501 "sm501" +#define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501) + +typedef struct { + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + SM501State state; + uint32_t vram_size; +} SM501PCIState; + +static void sm501_realize_pci(PCIDevice *dev, Error **errp) +{ + SM501PCIState *s = PCI_SM501(dev); + + sm501_init(&s->state, DEVICE(dev), s->vram_size); + if (get_local_mem_size(&s->state) != s->vram_size) { + error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32, + get_local_mem_size(&s->state)); + return; + } + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, + &s->state.local_mem_region); + pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, + &s->state.mmio_region); +} + +static Property sm501_pci_properties[] = { + DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sm501_reset_pci(DeviceState *dev) +{ + SM501PCIState *s = PCI_SM501(dev); + sm501_reset(&s->state); + /* Bits 2:0 of misc_control register is 001 for PCI */ + s->state.misc_control |= 1; +} + +static void sm501_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = sm501_realize_pci; + k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION; + k->device_id = PCI_DEVICE_ID_SM501; + k->class_id = PCI_CLASS_DISPLAY_OTHER; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); + dc->desc = "SM501 Display Controller"; + dc->props = sm501_pci_properties; + dc->reset = sm501_reset_pci; + dc->hotpluggable = false; +} + +static const TypeInfo sm501_pci_info = { + .name = TYPE_PCI_SM501, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(SM501PCIState), + .class_init = sm501_pci_class_init, +}; + static void sm501_register_types(void) { type_register_static(&sm501_sysbus_info); + type_register_static(&sm501_pci_info); } type_init(sm501_register_types) diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index d22ad8d..3752ddc 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -207,6 +207,9 @@ #define PCI_VENDOR_ID_MARVELL 0x11ab +#define PCI_VENDOR_ID_SILICON_MOTION 0x126f +#define PCI_DEVICE_ID_SM501 0x0501 + #define PCI_VENDOR_ID_ENSONIQ 0x1274 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000