From patchwork Wed Feb 17 19:09:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 8342371 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 371B69F399 for ; Wed, 17 Feb 2016 19:09:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 78C8F20394 for ; Wed, 17 Feb 2016 19:09:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 752D320386 for ; Wed, 17 Feb 2016 19:09:40 +0000 (UTC) Received: from localhost ([::1]:60743 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aW7Tn-0008Hj-OW for patchwork-qemu-devel@patchwork.kernel.org; Wed, 17 Feb 2016 14:09:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aW7TZ-0008Gu-Qh for qemu-devel@nongnu.org; Wed, 17 Feb 2016 14:09:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aW7TW-0003sf-Ie for qemu-devel@nongnu.org; Wed, 17 Feb 2016 14:09:25 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53099) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aW7TW-0003sY-BD; Wed, 17 Feb 2016 14:09:22 -0500 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id 023A619D239; Wed, 17 Feb 2016 19:09:21 +0000 (UTC) Received: from [10.10.52.181] (unused [10.10.52.181] (may be forged)) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u1HJ9KM5025302 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 17 Feb 2016 14:09:20 -0500 To: Peter Maydell References: <1454359775-25959-1-git-send-email-wei@redhat.com> <56C4AF0D.9070803@redhat.com> From: Wei Huang Message-ID: <56C4C55F.2050006@redhat.com> Date: Wed, 17 Feb 2016 13:09:19 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: QEMU Trivial , Igor Mammedov , Shannon Zhao , QEMU Developers , Shannon Zhao Subject: Re: [Qemu-devel] [PATCH V2 1/2] ARM: PL061: Clear PL061 device state after reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 02/17/2016 11:53 AM, Peter Maydell wrote: > On 17 February 2016 at 17:34, Wei Huang wrote: >> On 02/16/2016 08:39 AM, Peter Maydell wrote: >>> Side note: half our "PL061" behaviour is actually specific >>> to the TI variant in the Luminary, and for our plain old PL061 >>> we ought to restrict access to the registers that are Stellaris >>> only. But that's a different bug and not a very major one. >> >> Thanks for your suggestion. I was trying to fix it. The plan was to add >> a new field rsvd_addr in "struct PL061State". Then in pl061_read() and >> pl061_write(), we can check offset against [rsvd_addr, 0xfcc] (ignored >> if inside). >> >> While I was working on it, I realized that this is a benign issue. It is >> true that PL061 device can access Luminary registers in the reserved >> memory area. However QEMU doesn't use these Luminary registers anywhere >> else other than pl061_read() and pl061_write(). It basically passes the >> read/write requests through. I don't see a malicious driver can damage >> device state. Thoughts? > > It's not a "malicious guest can do bad things" bug, it's a "modelled > hardware doesn't behave like the real thing" bug. A non-Luminary PL061 > should act like the hardware, which means that the registers that don't > exist should be RAZ/WI (and should log guest-errors if the guest tries > to access them), the same way we do in the "default" case of the > case statements for other reserved registers. How about the attached patch? I can write a new patch based on it, or you prefer stashing it on top of V3 I just submitted? Thanks, -Wei > > thanks > -- PMM > diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 5ece8b0..03a6351 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -60,6 +60,7 @@ typedef struct PL061State { qemu_irq irq; qemu_irq out[8]; const unsigned char *id; + uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ } PL061State; static const VMStateDescription vmstate_pl061 = { @@ -158,6 +159,9 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, if (offset < 0x400) { return s->data & (offset >> 2); } + if (offset >= s->rsvd_start && offset <= 0xfcc) { + goto err_out; + } switch (offset) { case 0x400: /* Direction */ return s->dir; @@ -198,10 +202,12 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, case 0x528: /* Analog mode select */ return s->amsel; default: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_read: Bad offset %x\n", (int)offset); - return 0; + break; } +err_out: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_read: Bad offset %x\n", (int)offset); + return 0; } static void pl061_write(void *opaque, hwaddr offset, @@ -216,6 +222,9 @@ static void pl061_write(void *opaque, hwaddr offset, pl061_update(s); return; } + if (offset >= s->rsvd_start && offset <= 0xfcc) { + goto err_out; + } switch (offset) { case 0x400: /* Direction */ s->dir = value & 0xff; @@ -274,10 +283,14 @@ static void pl061_write(void *opaque, hwaddr offset, s->amsel = value & 0xff; break; default: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_write: Bad offset %x\n", (int)offset); + goto err_out; } pl061_update(s); + return; + +err_out: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_write: Bad offset %x\n", (int)offset); } static void pl061_reset(DeviceState *dev) @@ -347,6 +360,7 @@ static void pl061_luminary_init(Object *obj) PL061State *s = PL061(obj); s->id = pl061_id_luminary; + s->rsvd_start = 0x52c; } static void pl061_init(Object *obj) @@ -354,6 +368,7 @@ static void pl061_init(Object *obj) PL061State *s = PL061(obj); s->id = pl061_id; + s->rsvd_start = 0x424; } static void pl061_class_init(ObjectClass *klass, void *data)