From patchwork Sun Sep 11 14:54:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 9325435 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D84566077F for ; Sun, 11 Sep 2016 15:01:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C858F28A10 for ; Sun, 11 Sep 2016 15:01:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BAA2228A13; Sun, 11 Sep 2016 15:01:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0306228A10 for ; Sun, 11 Sep 2016 15:01:18 +0000 (UTC) Received: from localhost ([::1]:37929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bj6Fx-00015H-D1 for patchwork-qemu-devel@patchwork.kernel.org; Sun, 11 Sep 2016 11:01:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bj6Aq-0005W2-Qk for qemu-devel@nongnu.org; Sun, 11 Sep 2016 10:56:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bj6Al-0004Tl-R3 for qemu-devel@nongnu.org; Sun, 11 Sep 2016 10:55:59 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:33166) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bj6Al-0004Tf-Iy for qemu-devel@nongnu.org; Sun, 11 Sep 2016 10:55:55 -0400 Received: by mail-pf0-f193.google.com with SMTP id 128so6762458pfb.0 for ; Sun, 11 Sep 2016 07:55:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MtDcxvZgqXA+l0HK3j5z9WCSSDWNPbdWHpP3L4Xpjpc=; b=E6dGfd4LPSJfWNXlm+Ea/Cr7SFxXwdUKgBaDsfBqa473R3Ph2WRsD5FO/cMFkAwmrl n8rK0RPgeVMiuaQk0b9tXi+a+z1X9D2TXpQH9jV6RAhKt5Snkp3+2aSek4pCK1Zjm4Py H3vgkykVLMQVY07T3DAx95hVMZNNR0idYTNxBeN2vxR27wd1jCK8PBGbGORDxe4wYtXK 5Frbu6F2YgBpsIcYbV89Ogs900BH6vwsPwJrQ6zANqA+toX4HpEWc4hxcEU+krg7yAzf 2sJINZXDNjLbB2QB12W5Wo9a/kJr/dvOg7qKQWbC483NXOWBwo9As7pOqWrJTQ1HwCPs 46Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MtDcxvZgqXA+l0HK3j5z9WCSSDWNPbdWHpP3L4Xpjpc=; b=hCg0R6c8KOSHXCnwUsiLQI6iPUO710UgYdD4EjN1WMA4qDm/rifin2mzGf7nBAt7fS k594ruAFrqYSNKNvtJXJSCU1OPhL9LxOpDsNaOZXAIhRKXFIatUWcIfJmBxEz1wSnea6 4s4aqELs1ISPUQoXv5O1gpnNEsvtgc4SFclZ5ZNJY98h3rhHZNoL/0TgaOYBKipyLLXQ gChjAcGWLSf8AvDnZbYtx50RhaiMYUfxt8MfB4JlRmluLTezIxQTq4ApNjMWmWjdftZh dMhLcr9IX6tzQm3KHVhs3DfSk0JR5fjOIK+meAd/18hO6wHMf7HoXRmgsXF9oW3uFKQJ 3N4w== X-Gm-Message-State: AE9vXwP4ZGouMTwYqn4ylPT+BVyRESEE5EIhRGVeaI/7nJGfgkMgcI6pHSmxii2k2ylFSg== X-Received: by 10.98.220.93 with SMTP id t90mr1007191pfg.30.1473605694950; Sun, 11 Sep 2016 07:54:54 -0700 (PDT) Received: from localhost ([2601:646:8581:937e:2561:c199:6f8f:8bc8]) by smtp.gmail.com with ESMTPSA id g10sm18155929pfc.57.2016.09.11.07.54.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 11 Sep 2016 07:54:54 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 11 Sep 2016 07:54:53 -0700 Message-Id: <755eb3cc6df2c49ce500aa505b45ea043f632d4d.1473579576.git.alistair@alistair23.me> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.193 Subject: [Qemu-devel] [PATCH v7 6/8] STM32F205: Connect the ADC devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, konstanty@ieee.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Connect the ADC devices to the STM32F205 SoC. Signed-off-by: Alistair Francis --- V7: - Create the new ADC device V5: - Use the new irq ORing function V4: - Connect all the interrupt lines correctly V2: - Fix up the device/devices commit message hw/arm/stm32f205_soc.c | 36 ++++++++++++++++++++++++++++++++++++ include/hw/arm/stm32f205_soc.h | 6 ++++++ 2 files changed, 42 insertions(+) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 5b6fa3b..20c0754 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -34,9 +34,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 0x40000800, 0x40000C00 }; static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; +static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, + 0x40012200 }; static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; +#define ADC_IRQ 18 static void stm32f205_soc_initfn(Object *obj) { @@ -57,6 +60,14 @@ static void stm32f205_soc_initfn(Object *obj) TYPE_STM32F2XX_TIMER); qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); } + + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); + + for (i = 0; i < STM_NUM_ADCS; i++) { + object_initialize(&s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default()); + } } static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -64,6 +75,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) STM32F205State *s = STM32F205_SOC(dev_soc); DeviceState *dev, *nvic; SysBusDevice *busdev; + qemu_irq *gic_adc_irq_arr; Error *err = NULL; int i; @@ -132,6 +144,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_mmio_map(busdev, 0, timer_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i])); } + + /* ADC 1 to 3 */ + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, + "num-lines", &err); + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, + qdev_get_gpio_in(nvic, ADC_IRQ)); + gic_adc_irq_arr = qemu_get_or_irqs(DEVICE(s->adc_irqs)); + + for (i = 0; i < STM_NUM_ADCS; i++) { + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, adc_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gic_adc_irq_arr[i]); + } } static Property stm32f205_soc_properties[] = { diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 779b5da..1adf824 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -28,6 +28,8 @@ #include "hw/misc/stm32f2xx_syscfg.h" #include "hw/timer/stm32f2xx_timer.h" #include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" +#include "hw/or-irq.h" #define TYPE_STM32F205_SOC "stm32f205-soc" #define STM32F205_SOC(obj) \ @@ -35,6 +37,7 @@ #define STM_NUM_USARTS 6 #define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 3 #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) @@ -52,6 +55,9 @@ typedef struct STM32F205State { STM32F2XXSyscfgState syscfg; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; + STM32F2XXADCState adc[STM_NUM_ADCS]; + + qemu_or_irq *adc_irqs; } STM32F205State; #endif