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[124.44.184.64]) by smtp.gmail.com with ESMTPSA id u23sm26944455pfd.63.2017.04.23.15.41.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 23 Apr 2017 15:41:33 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Mon, 24 Apr 2017 07:40:56 +0900 Message-Id: <76adf807304af127f81f0c11f29b610b059f3497.1492986468.git.shorne@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::242 Subject: [Qemu-devel] [PATCH v2 8/9] target/openrisc: Implement full vmstate serialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , "Tim \\'mithro\\' Ansell" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Previously serialization did not persist the tlb, timer, pic and other key state items. This meant snapshotting and restoring a running os would crash. After adding these I am able to take snapshots of a running linux os and restore at a later time. I am currently not trying to maintain capatibility with older versions as I do not believe this really worked before or anyone used it. Signed-off-by: Stafford Horne --- Changes since v1: o Added evbar o Bumped version on vmstate_env target/openrisc/machine.c | 73 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 2bf71c3..a82be62 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,6 +24,63 @@ #include "hw/boards.h" #include "migration/cpu.h" +static int env_post_load(void *opaque, int version_id) +{ + CPUOpenRISCState *env = opaque; + + /* Restore MMU handlers */ + if (env->sr & SR_DME) { + env->tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_data; + } else { + env->tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_nommu; + } + + if (env->sr & SR_IME) { + env->tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_code; + } else { + env->tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_nommu; + } + + + return 0; +} + +static const VMStateDescription vmstate_tlb_entry = { + .name = "tlb_entry", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(mr, OpenRISCTLBEntry), + VMSTATE_UINTTL(tr, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_cpu_tlb = { + .name = "cpu_tlb", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, + ITLB_WAYS, ITLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, + DTLB_WAYS, DTLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +#define VMSTATE_CPU_TLB(_f, _s) \ + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) + + static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { CPUOpenRISCState *env = opaque; @@ -47,8 +104,9 @@ static const VMStateInfo vmstate_sr = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 5, - .minimum_version_id = 5, + .version_id = 6, + .minimum_version_id = 6, + .post_load = env_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), @@ -79,9 +137,20 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), + VMSTATE_UINT32(evbar, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), + + VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + + VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), + VMSTATE_UINT32(ttmr, CPUOpenRISCState), + VMSTATE_UINT32(ttcr, CPUOpenRISCState), + + VMSTATE_UINT32(picmr, CPUOpenRISCState), + VMSTATE_UINT32(picsr, CPUOpenRISCState), + VMSTATE_END_OF_LIST() } };