From patchwork Fri Sep 22 06:00:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nikunj A. Dadhania" X-Patchwork-Id: 9965195 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 705106020C for ; Fri, 22 Sep 2017 06:02:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6383821E5A for ; Fri, 22 Sep 2017 06:02:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 54A7F28D37; Fri, 22 Sep 2017 06:02:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8623121E5A for ; Fri, 22 Sep 2017 06:02:33 +0000 (UTC) Received: from localhost ([::1]:56795 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dvH2m-0002pg-9l for patchwork-qemu-devel@patchwork.kernel.org; Fri, 22 Sep 2017 02:02:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dvH1i-0002Vc-F7 for qemu-devel@nongnu.org; Fri, 22 Sep 2017 02:01:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dvH1f-0002QT-Px for qemu-devel@nongnu.org; Fri, 22 Sep 2017 02:01:26 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:34356 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dvH1f-0002Q3-L9 for qemu-devel@nongnu.org; Fri, 22 Sep 2017 02:01:23 -0400 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8M5DxBk100817 for ; Fri, 22 Sep 2017 02:01:19 -0400 Received: from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147]) by mx0b-001b2d01.pphosted.com with ESMTP id 2d4pnhk3q1-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 22 Sep 2017 02:01:18 -0400 Received: from localhost by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 22 Sep 2017 16:01:12 +1000 Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8M61CKa18808946; Fri, 22 Sep 2017 16:01:12 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v8M614mQ020854; Fri, 22 Sep 2017 16:01:04 +1000 Received: from abhimanyu.vnet.linux.ibm.com ([9.102.1.54]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v8M60iGg019774 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 22 Sep 2017 16:01:01 +1000 From: Nikunj A Dadhania To: David Gibson In-Reply-To: <20170921053107.GD4998@umbus.fritz.box> References: <20170919082421.GU27153@umbus> <871sn2hugn.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <20170920045524.GH5520@umbus.fritz.box> <87y3pagdg0.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <20170920061756.GJ5520@umbus.fritz.box> <87vakdhnyn.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <20170920065700.GO5520@umbus.fritz.box> <87poalhm74.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <20170920115342.GQ5520@umbus.fritz.box> <87377gpuyh.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> <20170921053107.GD4998@umbus.fritz.box> Date: Fri, 22 Sep 2017 11:30:51 +0530 MIME-Version: 1.0 X-TM-AS-MML: disable x-cbid: 17092206-0016-0000-0000-000002657372 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17092206-0017-0000-0000-000006EADB6E Message-Id: <87y3p7nugc.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-22_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709220072 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: Re: [Qemu-devel] [PATCH] ppc/pnv: fix cores per chip for multiple cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP David Gibson writes: >> >> >> >> As smp_thread defaults to 1 in vl.c, similarly smp_cores also has the >> >> default value of 1 in vl.c. In powernv, we were setting nr-cores like >> >> this: >> >> >> >> object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); >> >> >> >> Even when there were multiple cpus (-smp 4), when the guest boots up, we >> >> just get one core (i.e. smp_cores was 1) with single thread(smp_threads >> >> was 1), which is wrong as per the command-line that was provided. >> > >> > Right, so, -smp 4 defaults to 4 sockets, each with 1 core of 1 >> > thread. If you can't supply 4 sockets you should error, but you >> > shouldn't go and change the number of cores per socket. >> >> OK, that makes sense now. And I do see that smp_cpus is 4 in the above >> case. Now looking more into it, i see that powernv has something called >> "num_chips", isnt this same as sockets ? Do we need num_chips separately? > > Ah, yes, I see. It's probably still reasonable to keep num_chips as > an internal variable, rather than using (smp_cpus / smp_cores / > smp_threads) everywhere. But we shouldn't have it as a direct > user-settable property, instead setting it from the -smp command line > option. Something like the below works till num_chips=2, after that guest does not boot up. This might be some limitation within the OS, Cedric might have some clue. Otherwise, I see that multiple chips are created with single core having single thread. ppc/pnv: Use num_chips for multiple sockets When the user does not provide the cpu topology, e.g. "-smp 4", machine fails to initialize 4 cpus. QEMU assumes smp_threads and smp_cores both as 1. Make sure that we initialize multiple chips for this. Remove the user-settable property num_chips from machine command line option Signed-off-by: Nikunj A Dadhania diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 9724719..fa501f9 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -709,7 +709,17 @@ static void ppc_powernv_init(MachineState *machine) exit(1); } + pnv->num_chips = smp_cpus / (smp_cores * smp_threads); pnv->chips = g_new0(PnvChip *, pnv->num_chips); + + if (smp_cpus != (smp_threads * pnv->num_chips * smp_cores)) { + error_report("cpu topology not balanced: " + "chips (%u) * cores (%u) * threads (%u) != " + "number of cpus (%u)", + pnv->num_chips, smp_cores, smp_threads, smp_cpus); + exit(1); + } + for (i = 0; i < pnv->num_chips; i++) { char chip_name[32]; Object *chip = object_new(chip_typename); @@ -1255,53 +1265,12 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, } } -static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); -} - -static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - PnvMachineState *pnv = POWERNV_MACHINE(obj); - uint32_t num_chips; - Error *local_err = NULL; - - visit_type_uint32(v, name, &num_chips, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - /* - * TODO: should we decide on how many chips we can create based - * on #cores and Venice vs. Murano vs. Naples chip type etc..., - */ - if (!is_power_of_2(num_chips) || num_chips > 4) { - error_setg(errp, "invalid number of chips: '%d'", num_chips); - return; - } - - pnv->num_chips = num_chips; -} - static void powernv_machine_initfn(Object *obj) { PnvMachineState *pnv = POWERNV_MACHINE(obj); pnv->num_chips = 1; } -static void powernv_machine_class_props_init(ObjectClass *oc) -{ - object_class_property_add(oc, "num-chips", "uint32", - pnv_get_num_chips, pnv_set_num_chips, - NULL, NULL, NULL); - object_class_property_set_description(oc, "num-chips", - "Specifies the number of processor chips", - NULL); -} - static void powernv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1321,8 +1290,6 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data) xic->ics_get = pnv_ics_get; xic->ics_resend = pnv_ics_resend; ispc->print_info = pnv_pic_print_info; - - powernv_machine_class_props_init(oc); } static const TypeInfo powernv_machine_info = {