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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 00:29:36.5654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4176d2e-2eb2-4127-b7e4-08dc95770f20 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8185 Received-SPF: softfail client-ip=2a01:111:f403:2417::600; envelope-from=nicolinc@nvidia.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.151, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Nested SMMUv3 feature requires the support/presence of host-level SMMUv3 instance(s). Add a helper to read the sysfs for the number of instances. Log them in a vms list using a new struct VirtNestedSmmu. This will be used by a following patch to assign a passthrough device to corresponding nested SMMUv3 instance. Signed-off-by: Nicolin Chen --- hw/arm/virt.c | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 8 ++++++++ 2 files changed, 43 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 71093d7c60..be3d8b0ce6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2668,6 +2668,37 @@ static char *virt_get_iommu(Object *obj, Error **errp) } } +static int virt_get_num_nested_smmus(VirtMachineState *vms, Error **errp) +{ + VirtNestedSmmu *nested_smmu; + struct dirent *dent; + DIR *dir = NULL; + int num = 0; + + dir = opendir("/sys/class/iommu"); + if (!dir) { + error_setg_errno(errp, errno, "couldn't open /sys/class/iommu"); + return 0; + } + + while ((dent = readdir(dir))) { + if (!strncmp(dent->d_name, "smmu3.0x", 7)) { + nested_smmu = g_new0(VirtNestedSmmu, 1); + nested_smmu->index = num; + nested_smmu->smmu_node = g_strdup(dent->d_name); + QLIST_INSERT_HEAD(&vms->nested_smmu_list, nested_smmu, next); + num++; + } + } + + if (num == 0) { + error_setg_errno(errp, errno, + "couldn't find any SMMUv3 HW to setup nesting"); + } + + return num; +} + static void virt_set_iommu(Object *obj, const char *value, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -2676,6 +2707,7 @@ static void virt_set_iommu(Object *obj, const char *value, Error **errp) vms->iommu = VIRT_IOMMU_SMMUV3; } else if (!strcmp(value, "nested-smmuv3")) { vms->iommu = VIRT_IOMMU_NESTED_SMMUV3; + vms->num_nested_smmus = virt_get_num_nested_smmus(vms, errp); } else if (!strcmp(value, "none")) { vms->iommu = VIRT_IOMMU_NONE; } else { @@ -3232,6 +3264,9 @@ static void virt_instance_init(Object *obj) /* The default root bus is attached to iommu by default */ vms->default_bus_bypass_iommu = false; + /* Default disallows nested SMMU instantiation */ + vms->num_nested_smmus = 0; + /* Default disallows RAS instantiation */ vms->ras = false; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index d5cbce1a30..e0c07527c4 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -135,6 +135,12 @@ struct VirtMachineClass { bool no_ns_el2_virt_timer_irq; }; +typedef struct VirtNestedSmmu { + int index; + char *smmu_node; + QLIST_ENTRY(VirtNestedSmmu) next; +} VirtNestedSmmu; + struct VirtMachineState { MachineState parent; Notifier machine_done; @@ -153,6 +159,7 @@ struct VirtMachineState { bool ras; bool mte; bool dtb_randomness; + int num_nested_smmus; OnOffAuto acpi; VirtGICType gic_version; IOMMUFDBackend *iommufd; @@ -178,6 +185,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + QLIST_HEAD(, VirtNestedSmmu) nested_smmu_list; }; #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)