From patchwork Tue Dec 6 23:06:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Evans X-Patchwork-Id: 9463441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BA46260231 for ; Tue, 6 Dec 2016 23:08:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2B70284C3 for ; Tue, 6 Dec 2016 23:08:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95F03284F7; Tue, 6 Dec 2016 23:08:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0B299284C3 for ; Tue, 6 Dec 2016 23:08:17 +0000 (UTC) Received: from localhost ([::1]:35426 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cEOqO-0003As-EK for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Dec 2016 18:08:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56071) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <3dkRHWAMKCuMIOJLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--dje.bounces.google.com>) id 1cEOq6-0003AV-D3 for qemu-devel@nongnu.org; Tue, 06 Dec 2016 18:07:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <3dkRHWAMKCuMIOJLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--dje.bounces.google.com>) id 1cEOq1-0001OH-F9 for qemu-devel@nongnu.org; Tue, 06 Dec 2016 18:07:58 -0500 Received: from mail-pf0-f202.google.com ([209.85.192.202]:33842) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from <3dkRHWAMKCuMIOJLTTLQJ.HTRVJRZ-IJaJQSTSLSZ.TWL@flex--dje.bounces.google.com>) id 1cEOq1-0001Cp-7z for qemu-devel@nongnu.org; Tue, 06 Dec 2016 18:07:53 -0500 Received: by mail-pf0-f202.google.com with SMTP id a8so13736912pfg.1 for ; Tue, 06 Dec 2016 15:07:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:message-id:date:subject:from:to; bh=HoWhV5SqcAZ3BHd5313AmkcoG0PVBKsrJRSkfyiWALs=; b=GkosD1jmyAyo+jMNjVfw3GqDFwMLERmMc/knFeL5fhpDk9QTL2+cjOunRIvalvdd2Q H8XGnwAPF6rDNzZJM9dL3Pwxl8QxwQqBFJvE3TjJCsGy6YfhRyqyLGhOu8WwHwXXIhF5 jK3hbEXtM5tIRPReSVWcv4x2cBbJMCO+mex9m3ykESzOrn7fYkmIAd3ijiA5kRQ2s7g/ ELenHfRnaz0LsYsjc/E7V9E8V83lXLMY7E2J3UFg9jdAULmVzgBFQQzrk8g/Ng+Gfhgh 7BB/u6sv9XQGlYPTrhwkaDR3vzsdWPeqeh1wutLnFh03nmbty7veO1ITCrYjQVFsd92/ dElw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:message-id:date:subject:from:to; bh=HoWhV5SqcAZ3BHd5313AmkcoG0PVBKsrJRSkfyiWALs=; b=GRS5bdII2xsELEqWQKiYCpbbtz3a+tmNp3z2ltKuvTOzNH0JArMPzTOTVqv8lL4h6X d366gCemvyi5QOt02DTy+c93u1YFd+tAWwNs4ELkCxHXyBTactHCbF/cFY4ixB99ADmh K/9Dqi+dukn7od+u7IySioX0mgYka7Ijpl0mS01riEdkx+ZSynji6+K7BZNoC98sSCAv 7Y0z4LPJr1+e+Gw7h/l5iQ8GGmC8n2xHGnQ5CT9KgAzZcUdDIIP2vZB2+WV66e6XDTGS 0G9o6sxVdtlSnLD4Il/8CV5PIPJpZ282LDqsJfOxr7hLKhoJh9mcb5SPlEg+L+hOOViG Gnfg== X-Gm-Message-State: AKaTC03EATXntltxQzeOAFfLxRPpgzS/X0jU+nSPvme/iwqYbTARVvMbrrCYdC/8nHIeKx0HJSGuuPppDKi2psTKJzDJYUvXyPWtkOXyOVJcpAeADP2NVBP+xLVxSvUXfL+JRT8LrgjnSr68JDbRLlHFnYSa54Dw22WRvAU1H6gQSp0= MIME-Version: 1.0 X-Received: by 10.98.48.68 with SMTP id w65mr12373345pfw.15.1481065590567; Tue, 06 Dec 2016 15:06:30 -0800 (PST) Message-ID: <94eb2c0bfa1c6a9fec0543057483@google.com> Date: Tue, 06 Dec 2016 23:06:30 +0000 From: Doug Evans To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.202 Subject: [Qemu-devel] [PATCH] target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hi. While qemu's behaviour matches what one would expect from reading the docs, it does not match what I'm seeing on h/w. Can anyone else confirm what the correct behaviour is here? --- The syscall and sysret instructions behave a bit differently: TF is checked after the instruction completes. This allows the o/s to disable #DB at a syscall by adding TF to FMASK. And then when the sysret is executed the #DB is taken "as if" the syscall insn just completed. Signed-off-by: Doug Evans --- target-i386/bpt_helper.c | 12 ++++++++++++ target-i386/helper.h | 1 + target-i386/translate.c | 29 ++++++++++++++++++++++++----- 3 files changed, 37 insertions(+), 5 deletions(-) } else { @@ -2525,10 +2530,17 @@ static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit) s->is_jmp = DISAS_TB_JUMP; } +/* End of block. + If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set. */ +static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit) +{ + gen_eob_worker(s, inhibit, false); +} + /* End of block, resetting the inhibit irq flag. */ static void gen_eob(DisasContext *s) { - gen_eob_inhibit_irq(s, false); + gen_eob_worker(s, false, false); } /* generate a jump to eip. No segment change must happen before as a @@ -7108,7 +7120,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (s->lma) { set_cc_op(s, CC_OP_EFLAGS); } - gen_eob(s); + /* TF handling for the syscall insn is different. The TF bit is checked + after the syscall insn completes. This allows #DB to not be + generated after one has entered CPL0 if TF is set in FMASK. */ + gen_eob_worker(s, false, true); break; case 0x107: /* sysret */ if (!s->pe) { @@ -7119,7 +7134,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (s->lma) { set_cc_op(s, CC_OP_EFLAGS); } - gen_eob(s); + /* TF handling for the sysret insn is different. The TF bit is + checked after the sysret insn completes. This allows #DB to be + generated "as if" the syscall insn in userspace has just + completed. */ + gen_eob_worker(s, false, true); } break; #endif diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c index 6fd7fe0..d771461 100644 --- a/target-i386/bpt_helper.c +++ b/target-i386/bpt_helper.c @@ -244,6 +244,18 @@ void helper_single_step(CPUX86State *env) raise_exception(env, EXCP01_DB); } +void helper_rechecking_single_step(CPUX86State *env) +{ + if ((env->eflags & TF_MASK) != 0) + { +#ifndef CONFIG_USER_ONLY + check_hw_breakpoints(env, true); + env->dr[6] |= DR6_BS; +#endif + raise_exception(env, EXCP01_DB); + } +} + void helper_set_dr(CPUX86State *env, int reg, target_ulong t0) { #ifndef CONFIG_USER_ONLY diff --git a/target-i386/helper.h b/target-i386/helper.h index 4e859eb..bd9b2cf 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -79,6 +79,7 @@ DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) #endif DEF_HELPER_1(single_step, void, env) +DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) DEF_HELPER_1(rdtsc, void, env) DEF_HELPER_1(rdtscp, void, env) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9fd1a04..42d036e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2500,8 +2500,10 @@ static void gen_bnd_jmp(DisasContext *s) } /* Generate an end of block. Trace exception is also generated if needed. - If IIM, set HF_INHIBIT_IRQ_MASK if it isn't already set. */ -static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit) + If INHIBIT, set HF_INHIBIT_IRQ_MASK if it isn't already set. + If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of + S->TF. This is used by the syscall/sysret insns. */ +static void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf) { gen_update_cc_op(s); @@ -2517,6 +2519,9 @@ static void gen_eob_inhibit_irq(DisasContext *s, bool inhibit) } if (s->singlestep_enabled) { gen_helper_debug(cpu_env); + } else if (recheck_tf) { + gen_helper_rechecking_single_step(cpu_env); + tcg_gen_exit_tb(0); } else if (s->tf) { gen_helper_single_step(cpu_env);