diff mbox series

[v2,8/8] target/mips: Enable MSA ASE for mips64R2-generic

Message ID AM9PR09MB485141F5613A7EBFC5A4A08884402@AM9PR09MB4851.eurprd09.prod.outlook.com (mailing list archive)
State New
Headers show
Series [v2,1/8] Add CP0 MemoryMapID register implementation | expand

Commit Message

Aleksandar Rakic Oct. 18, 2024, 1:21 p.m. UTC 
Enable MSA ASE for mips64R2-generic CPU.

Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f
from  https://github.com/MIPS/gnutools-qemu

Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 target/mips/cpu-defs.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Aleksandar Rikalo Oct. 19, 2024, 7:54 a.m. UTC | #1 
>
> Enable MSA ASE for mips64R2-generic CPU.
>
> Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f
> from  https://github.com/MIPS/gnutools-qemu
>
> Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
>  target/mips/cpu-defs.c.inc | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

R2 CPUs usually don't support MSA, I think we should skip this.

-- Aleksandar
Philippe Mathieu-Daudé Oct. 25, 2024, 7:24 p.m. UTC | #2 
On 18/10/24 10:21, Aleksandar Rakic wrote:
> Enable MSA ASE for mips64R2-generic CPU.
> 
> Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f
> from  https://github.com/MIPS/gnutools-qemu
> 
> Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
>   target/mips/cpu-defs.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 19e2abac82..2b707cc5a7 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -678,7 +678,9 @@ const mips_def_t mips_defs[] =
>                          (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>                          (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>           .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) |
> +                       (1 << CP0C3_VInt) | (1 << CP0C3_MSAP),
> +        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),
>           .CP0_LLAddr_rw_bitmask = 0,
>           .CP0_LLAddr_shift = 0,
>           .SYNCI_Step = 32,

We already have the I6400/I6500 which are R6 with MSA.

Why would we need a non-R6 core with MSA?
diff mbox series

Patch

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 19e2abac82..2b707cc5a7 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -678,7 +678,9 @@  const mips_def_t mips_defs[] =
                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) |
+                       (1 << CP0C3_VInt) | (1 << CP0C3_MSAP),
+        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),
         .CP0_LLAddr_rw_bitmask = 0,
         .CP0_LLAddr_shift = 0,
         .SYNCI_Step = 32,