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Fri, 18 Oct 2024 13:20:58 +0000 From: Aleksandar Rakic To: "qemu-devel@nongnu.org" CC: Djordje Todorovic , "cfu@mips.com" , "arikalo@gmail.com" , "peter.maydell@linaro.org" Subject: [PATCH v2 7/8] target/mips: Enable MSA ASE for mips32r6-generic Thread-Topic: [PATCH v2 7/8] target/mips: Enable MSA ASE for mips32r6-generic Thread-Index: AQHbIV6ZcJEdOYNeb0KRrafnu7qlXg== Date: Fri, 18 Oct 2024 13:20:58 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: AM9PR09MB4851:EE_|AS8PR09MB6210:EE_ x-ms-office365-filtering-correlation-id: 21df66e0-cdea-4275-00e7-08dcef77b472 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|366016|376014|1800799024|38070700018; x-microsoft-antispam-message-info: =?iso-8859-1?q?19tTkFkexNmD4abPmvTDAmoHoX?= =?iso-8859-1?q?n/sbPxHGewdoTXatj3OcVvVmP4Awztx0+JZFER0sduQndIAPzRs8+ACalMG4?= =?iso-8859-1?q?oVXba7CI1c8BqGqQ9sn1myMD0nC1oWID1rjMQYo5LsktdiPDkb5Lzu4YEk6T?= =?iso-8859-1?q?cNoMxqpQXdqQVTMvYmBvHLnOiNf3OU+cGw93cebzjnu0yWWXCeZqsU6OLVuC?= =?iso-8859-1?q?AYEUTxpN4FnyD/XU7Vuy7z1Qp2ht8yCUCH2fhHhg/agjMyFxOZGr4ZVnJj/r?= =?iso-8859-1?q?JQCyNOBM9DEpac43ktUhinw9RyJ273xLyoEmEJJEjXuGVB/5LcuDflfBEb2P?= =?iso-8859-1?q?WINHeOTBs04WaIdukcV6XmrfYgpSvNfvZszmvXWgxQG4wdaAG2iTcCt2Fhmz?= =?iso-8859-1?q?tbQjOue/s1k6HHuFQOhmsZncWte1O2PaPJbHGNS8nIRrq/BbzouUSBAyIxDM?= =?iso-8859-1?q?C53rP3xg8FnMr6zuVGQQslJ6+YD0+YWwafAF4WwVyo9G9tDZmvXEUTvB6O4S?= =?iso-8859-1?q?MBQHT7I6X98yd2vIrycDGvAG9nOATGcTIYBPWzZO15zbxOba12BLNUZ/T0/M?= =?iso-8859-1?q?I7praqxWGXdACT7Sq9bA7mdK4Fql16Pb05SZYEwOnowx29z/epd9CT9UFTCR?= =?iso-8859-1?q?TyOzGSKaZ3pGUIqV6kK4Uqc/hEuBaE9PLtsep7bICbNOHWeK12mqipVkZJjG?= =?iso-8859-1?q?zMsdhKm8HdDTE0utrQ7hagloJCpzjzi1Nu6bCkC83NW1k0c9/l0Vax9JNWa7?= =?iso-8859-1?q?YtvkesY/Vmhu5jbU8lDamzFQkQdqlHt1yswlIqSXS/fBb+uTS46qvSjkyjwh?= =?iso-8859-1?q?fUsbKhEo2J9RQ+m/1urGE7CyiEJSs7wG0TYnhQbIUbO7bT2p9thwiwPb8WlE?= =?iso-8859-1?q?e8ZBDQ79kJm+sCFVYYlzaqQXbIJ4PPzzZ1kEa0/uQhF0Sm3wiwqJJqA8LqqO?= =?iso-8859-1?q?j/Wk3b9wWj/M1pu12VBkmzw4mTx5W4V+08YgRHnPJge8dOxwkfw1y7Y7h1X8?= =?iso-8859-1?q?AjA6dwjjnTTf+4siCfTHlA5vjM0OgfZJrCHW2jCojUcDmLYg6UzDrg8AmEtL?= =?iso-8859-1?q?Sn3uaAbB2RQ48Q6+l69TTI/BnN0/xUbap3QCaV/UDlGnt9rTGpzna+u2N5pl?= =?iso-8859-1?q?Jr3CyVlRC+R1M54gz7UaXsIDIjw268uIrLDfFeZsQD480cG5dDSHRZjYdaLk?= =?iso-8859-1?q?MivvD6uePkIVMGbtGq7Av2fE/wGsQ/4Xx33QBNeXYeAwL2784FqgPN9i4OGn?= =?iso-8859-1?q?vB4SM+TaG7ORnPoT//wL9vjp9X7rIroYee7NP9xfj2feVwn7mnzGorBZ0tiM?= =?iso-8859-1?q?cRzCDwbS/CvmSy+X7+SOZ91YURdWRXEesuabxpBNxEKmW/tJoA/5VSC6ry0K?= =?iso-8859-1?q?AwG1+MxibUworNZmYMmEtldQjbFJ8uvDTrPMl22mRivqNcwbX2pW8pQ+I4oX?= =?iso-8859-1?q?Wg?= x-forefront-antispam-report: CIP:255.255.255.255; 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envelope-from=aleksandar.rakic@htecgroup.com; helo=EUR05-VI1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable MSA ASE for mips32r6-generic CPU. Cherry-picked 0186e83a0613e90aff6d4c12c91cdb080d695d37 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Aleksandar Markovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Reviewed-by: Aleksandar Rikalo --- target/mips/cpu-defs.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 9428ece220..19e2abac82 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -478,14 +478,15 @@ const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1U << CP0C3_M), .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1U << CP0C4_M), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, @@ -499,6 +500,7 @@ const mips_def_t mips_defs[] = (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .MSAIR = 0x03 << MSAIR_ProcID, .SEGBITS = 32, .PABITS = 32, .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,