[v5,00/10] tcg mips64 and mips r6 improvements

Commit Message

YunQiang Su Dec. 2, 2016, 7:30 a.m. UTC

I tested this patch set on MIPS EB.

1) MIPS r2:

(HOST)          (qemu-system)                   (Debian ISO)
64eb      ->     i386                      ->           i386
64eb      ->     x86_64                 ->           i386
64eb      ->     x86_64                 ->           amd64
n32eb    ->     i386                      ->           i386
n32eb    ->     x86_64                 ->           i386
n32eb    ->     x86_64                 ->           amd64
32eb      ->     i386                      ->           i386
32eb      ->     x86_64                 ->           i386
32eb      ->     x86_64                 ->           amd64

2) On r2 CPU,  with disable
          use_movnz_instructions
          use_mips32_instructions
          use_mips32r2_instructions
    See the attached file.

(HOST)          (qemu-system)                   (Debian ISO)
64eb      ->     i386                      ->           i386
64eb      ->     x86_64                 ->           i386
64eb      ->     x86_64                 ->           amd64
n32eb    ->     i386                      ->           i386
n32eb    ->     x86_64                 ->           i386
n32eb    ->     x86_64                 ->           amd64
32eb      ->     i386                      ->           i386
32eb      ->     x86_64                 ->           i386
32eb      ->     x86_64                 ->           amd64

If needed, I can also help to test other cases.

Patch

diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index d352c97..d467dde 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -90,21 +90,24 @@  typedef enum {
 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
     defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
     defined(_MIPS_ARCH_MIPS4)
-#define use_movnz_instructions  1
+//#define use_movnz_instructions  1
+extern bool use_movnz_instructions;
 #else
 extern bool use_movnz_instructions;
 #endif
 
 /* MIPS32 instruction set detection */
 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
-#define use_mips32_instructions  1
+//#define use_mips32_instructions  1
+extern bool use_mips32_instructions;
 #else
 extern bool use_mips32_instructions;
 #endif
 
 /* MIPS32R2 instruction set detection */
 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
-#define use_mips32r2_instructions  1
+//#define use_mips32r2_instructions  1
+extern bool use_mips32r2_instructions;
 #else
 extern bool use_mips32r2_instructions;
 #endif
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index e6479e4..ab86b3b 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -2309,7 +2309,8 @@  static void tcg_target_detect_isa(void)
                  "movz $zero, $zero, $zero\n"
                  ".set pop\n"
                  : : : );
-    use_movnz_instructions = !got_sigill;
+    //use_movnz_instructions = !got_sigill;
+    use_movnz_instructions = 0;
 #endif
 
     /* Probe for MIPS32 instructions. As no subsetting is allowed
@@ -2322,7 +2323,8 @@  static void tcg_target_detect_isa(void)
                  "mul $zero, $zero\n"
                  ".set pop\n"
                  : : : );
-    use_mips32_instructions = !got_sigill;
+    //use_mips32_instructions = !got_sigill;
+    use_mips32_instructions = 0;
 #endif
 
     /* Probe for MIPS32r2 instructions if MIPS32 instructions are
@@ -2336,7 +2338,8 @@  static void tcg_target_detect_isa(void)
                      "seb $zero, $zero\n"
                      ".set pop\n"
                      : : : );
-        use_mips32r2_instructions = !got_sigill;
+        //use_mips32r2_instructions = !got_sigill;
+        use_mips32r2_instructions = 0;
     }
 #endif