| Message ID | F41EE8A3-CF56-463C-A409-04BD616AD3BC@dmllr.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Andreas, Am 09.02.2016 um 21:59 schrieb Dirk Müller: > This is used by the ARM JTAG DCC console in the Linux kernel, > but can be ignored in order to continue booting. > > Co-Authored-By: Andreas Schwab <schwab@suse.de> If this was co-authored by you, we need a proper Signed-off-by please. > Signed-off-by: Dirk Mueller <dmueller@suse.com> > --- > target-arm/helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 954e6e8..abce416 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3704,6 +3704,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > { .name = "DBGVCR", > .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_NOP }, > + { .name = "DBGDTRxX_EL0", .state = ARM_CP_STATE_BOTH, > + .cp = 14, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0, > + .access = PL0_RW, .type = ARM_CP_NOP }, > REGINFO_SENTINEL > }; > Otherwise this can have my Reviewed-by. The small x was suggested by me since it's actually RX/TX depending on R/W. Regards, Andreas
On 9 February 2016 at 20:59, Dirk Müller <dirk@dmllr.de> wrote: > This is used by the ARM JTAG DCC console in the Linux kernel, > but can be ignored in order to continue booting. > > Co-Authored-By: Andreas Schwab <schwab@suse.de> > Signed-off-by: Dirk Mueller <dmueller@suse.com> > --- > target-arm/helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 954e6e8..abce416 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3704,6 +3704,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > { .name = "DBGVCR", > .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_NOP }, > + { .name = "DBGDTRxX_EL0", .state = ARM_CP_STATE_BOTH, > + .cp = 14, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0, You've marked the register as STATE_BOTH, but this is the wrong encoding for the AArch32 version (which has opc1 = 0); you'll need to split into one regdef for each. > + .access = PL0_RW, .type = ARM_CP_NOP }, > REGINFO_SENTINEL > }; Can you also add an access function for this register, please? https://git.linaro.org/people/peter.maydell/qemu-arm.git target-arm.next has the patches I sent recently that implement the MDCR_EL*.TDA traps, and this new register is in the same category. Minimum requirement: use access_tda() and add a comment that we don't implement the configurable EL0 traps. (this is what we do for MDCCSR_EL0 at the moment). Optional extra: implement a new access_tdcc() which checks for the MDSCR_EL1.TDCC trap and the MDCR_EL2.TDA and MDCR_EL3.TDA traps, and use that. (Bonus points: then use that access function on the other couple of registers which need it.) thanks -- PMM
diff --git a/target-arm/helper.c b/target-arm/helper.c index 954e6e8..abce416 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3704,6 +3704,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { { .name = "DBGVCR", .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, + { .name = "DBGDTRxX_EL0", .state = ARM_CP_STATE_BOTH, + .cp = 14, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0, + .access = PL0_RW, .type = ARM_CP_NOP }, REGINFO_SENTINEL };
This is used by the ARM JTAG DCC console in the Linux kernel, but can be ignored in order to continue booting. Co-Authored-By: Andreas Schwab <schwab@suse.de> Signed-off-by: Dirk Mueller <dmueller@suse.com> --- target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+)