From patchwork Sat Jun 9 12:07:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 10455499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E6BF9601D4 for ; Sat, 9 Jun 2018 12:08:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA00420700 for ; Sat, 9 Jun 2018 12:08:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD9F8223A4; Sat, 9 Jun 2018 12:08:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EFFD320700 for ; Sat, 9 Jun 2018 12:08:05 +0000 (UTC) Received: from localhost ([::1]:40187 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRcf6-0003Pl-Ka for patchwork-qemu-devel@patchwork.kernel.org; Sat, 09 Jun 2018 08:08:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43572) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fRceL-00032X-E6 for qemu-devel@nongnu.org; Sat, 09 Jun 2018 08:07:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fRceI-0007rf-91 for qemu-devel@nongnu.org; Sat, 09 Jun 2018 08:07:17 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:54367) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fRceH-0007pN-Ur; Sat, 09 Jun 2018 08:07:14 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 2B0967456E7; Sat, 9 Jun 2018 14:07:12 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id CA4177456D4; Sat, 9 Jun 2018 14:07:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id C40B87456B9; Sat, 9 Jun 2018 14:07:11 +0200 (CEST) Date: Sat, 9 Jun 2018 14:07:11 +0200 (CEST) From: BALATON Zoltan To: qemu-devel@nongnu.org In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21 (BSF 202 2017-01-01) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: Re: [Qemu-devel] [Qemu-ppc] icbt on PPC440 after commit 01662f3e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On Sat, 2 Jun 2018, BALATON Zoltan wrote: > I get an invalid instruction exception for the icbt instruction on the > sam460ex machine (PPC440 core 460EX CPU) but I think this should not raise > exception as it's valid on BookE that this CPU should support. Commit > 01662f3e PPC: Implement e500 (FSL) MMU has introduced an extended instruction > type (type2) in PPC opcodes and changed taget/ppc/translate_init.c as: > > @@ -9437,7 +9492,8 @@ static int create_ppc_opcodes (CPUPPCState *env, const > ppc_def_t *def) > > fill_new_table(env->opcodes, 0x40); > for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { > - if ((opc->handler.type & def->insns_flags) != 0) { > + if (((opc->handler.type & def->insns_flags) != 0) || > + ((opc->handler.type2 & def->insns_flags2) != 0)) { > if (register_insn(env->opcodes, opc) < 0) { > printf("*** ERROR initializing PowerPC instruction " > "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2, > > > it also made this change in target/ppc/translate.c: > > -GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE), > -GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), > -GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE), > +GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, > + PPC_BOOKE, PPC2_BOOKE206), > +GEN_HANDLER_E(msync, 0x1F, 0x16, 0x12, 0x03FFF801, > + PPC_BOOKE, PPC2_BOOKE206), > +GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, > + PPC_BOOKE, PPC2_BOOKE206), > > If I revert this change to icbt_440 it works without exception but according > to the above it should also work for either type == BOOKE _or_ type2 == > BOOKE206 but I still get exception in that case. Any idea why is this not > working as expected? This has gone for a while but then happened again and this time I've found that icbt seems to have two opcodes on PPC440 and got invalid instruction exception for 7c063a0c (1f-06-08-06) now. Not sure why I got it for other opcode or I was decoding it wrong that time but the problem I saw now could be fixed by Can anyone confirm that's correct? If so I'll include in my next series. Regards, BALATON Zoltan diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b28e8b9..40bc02d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6699,6 +6699,8 @@ GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, + PPC_440_SPEC), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),