From patchwork Sat Apr 2 13:15:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 8731461 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 15A22C0553 for ; Sat, 2 Apr 2016 13:15:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 470C52037E for ; Sat, 2 Apr 2016 13:15:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2482C20328 for ; Sat, 2 Apr 2016 13:15:26 +0000 (UTC) Received: from localhost ([::1]:49570 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1amLOf-0001jL-5V for patchwork-qemu-devel@patchwork.kernel.org; Sat, 02 Apr 2016 09:15:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52032) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1amLOX-0001jG-7f for qemu-devel@nongnu.org; Sat, 02 Apr 2016 09:15:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1amLOU-0005PX-1M for qemu-devel@nongnu.org; Sat, 02 Apr 2016 09:15:17 -0400 Received: from zose-mta03.web4all.fr ([185.49.20.44]:37338) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1amLOT-0005PS-No for qemu-devel@nongnu.org; Sat, 02 Apr 2016 09:15:13 -0400 Received: from localhost (localhost [127.0.0.1]) by zose-mta03.web4all.fr (Postfix) with ESMTP id 16D5D4162C; Sat, 2 Apr 2016 15:15:11 +0200 (CEST) Received: from zose-mta03.web4all.fr ([127.0.0.1]) by localhost (zose-mta03.web4all.fr [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id htDTeUXi4IR5; Sat, 2 Apr 2016 15:15:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta03.web4all.fr (Postfix) with ESMTP id 6AFD741DC4; Sat, 2 Apr 2016 15:15:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose-mta-03.w4a.fr Received: from zose-mta03.web4all.fr ([127.0.0.1]) by localhost (zose-mta03.web4all.fr [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id NgoGml1YtvGU; Sat, 2 Apr 2016 15:15:10 +0200 (CEST) Received: from localhost.localdomain (smm49-1-78-235-240-156.fbx.proxad.net [78.235.240.156]) by zose-mta03.web4all.fr (Postfix) with ESMTPSA id 1E2EE41C80; Sat, 2 Apr 2016 15:15:10 +0200 (CEST) From: Jean-Christophe Dubois To: qemu-devel@nongnu.org, peter.maydell@linaro.org, crosthwaite.peter@gmail.com Date: Sat, 2 Apr 2016 15:15:07 +0200 Message-Id: X-Mailer: git-send-email 2.5.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 185.49.20.44 Cc: Jean-Christophe Dubois Subject: [Qemu-devel] [PATCH v6 6/6] i.MX: Add sabrelite i.MX6 emulation. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The sabrelite supports one SPI FLASH memory on SPI1 Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * Output a message and exit if RAM size is unsupported. Changes since V2: * Added include "qemu/osdep.h" * Added access to controllers through properties. Changes since V3: * None Changes since V4: * Added a TODO. Changes since V5: * None hw/arm/Makefile.objs | 2 +- hw/arm/sabrelite.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 hw/arm/sabrelite.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 2b20e49..12764ef 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -16,5 +16,5 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o -obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o +obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) += ast2400.o palmetto-bmc.o diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c new file mode 100644 index 0000000..4037327 --- /dev/null +++ b/hw/arm/sabrelite.c @@ -0,0 +1,122 @@ +/* + * SABRELITE Board System emulation. + * + * Copyright (c) 2015 Jean-Christophe Dubois + * + * This code is licensed under the GPL, version 2 or later. + * See the file `COPYING' in the top level directory. + * + * It (partially) emulates a sabrelite board, with a Freescale + * i.MX6 SoC + */ + +#include "qemu/osdep.h" +#include "hw/arm/fsl-imx6.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "exec/address-spaces.h" +#include "net/net.h" +#include "hw/devices.h" +#include "hw/char/serial.h" +#include "sysemu/qtest.h" + +typedef struct IMX6Sabrelite { + FslIMX6State soc; + MemoryRegion ram; +} IMX6Sabrelite; + +static struct arm_boot_info sabrelite_binfo = { + /* DDR memory start */ + .loader_start = FSL_IMX6_MMDC_ADDR, + /* No board ID, we boot from DT tree */ + .board_id = -1, +}; + +/* No need to do any particular setup for secondary boot */ +static void sabrelite_write_secondary(ARMCPU *cpu, + const struct arm_boot_info *info) +{ +} + +/* Secondary cores are reset through SRC device */ +static void sabrelite_reset_secondary(ARMCPU *cpu, + const struct arm_boot_info *info) +{ +} + +static void sabrelite_init(MachineState *machine) +{ + IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1); + Error *err = NULL; + + /* Check the amount of memory is compatible with the SOC */ + if (machine->ram_size > FSL_IMX6_MMDC_SIZE) { + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)", + machine->ram_size, FSL_IMX6_MMDC_SIZE); + exit(1); + } + + object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX6); + object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), + &error_abort); + + object_property_set_bool(OBJECT(&s->soc), true, "realized", &err); + if (err != NULL) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + + memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram", + machine->ram_size); + memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, + &s->ram); + + { + /* + * TODO: Ideally we would expose the chip select and spi bus on the + * SoC object using alias properties; then we would not need to + * directly access the underlying spi device object. + */ + /* Add the sst25vf016b NOR FLASH memory to first SPI */ + Object *spi_dev; + + spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1"); + if (spi_dev) { + SSIBus *spi_bus; + + spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi"); + if (spi_bus) { + DeviceState *flash_dev; + + flash_dev = ssi_create_slave(spi_bus, "sst25vf016b"); + if (flash_dev) { + qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev, + SSI_GPIO_CS, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line); + } + } + } + } + + sabrelite_binfo.ram_size = machine->ram_size; + sabrelite_binfo.kernel_filename = machine->kernel_filename; + sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline; + sabrelite_binfo.initrd_filename = machine->initrd_filename; + sabrelite_binfo.nb_cpus = smp_cpus; + sabrelite_binfo.secure_boot = true; + sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary; + sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary; + + if (!qtest_enabled()) { + arm_load_kernel(&s->soc.cpu[0], &sabrelite_binfo); + } +} + +static void sabrelite_machine_init(MachineClass *mc) +{ + mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; + mc->init = sabrelite_init; + mc->max_cpus = FSL_IMX6_NUM_CPUS; +} + +DEFINE_MACHINE("sabrelite", sabrelite_machine_init)