From patchwork Fri Aug 24 19:44:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Denis V. Lunev\" via" X-Patchwork-Id: 10575903 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20ECC920 for ; Fri, 24 Aug 2018 20:54:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F66C2CCDE for ; Fri, 24 Aug 2018 20:54:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 017AC2CCE6; Fri, 24 Aug 2018 20:54:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 888B42CCE0 for ; Fri, 24 Aug 2018 20:54:33 +0000 (UTC) Received: from localhost ([::1]:43622 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftJ6G-0006TD-Es for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 Aug 2018 16:54:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftI57-0001Ku-5i for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:49:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ftI53-0007ms-FP for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:49:17 -0400 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:29927) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ftI53-0007mI-67 for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:49:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535140151; x=1566676151; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Am8lNM1YcJjKAIvP99qd9APR4nYaa/ED6qhNI9qfSvM=; b=Qsov5tNkdI6/yNkRSs2RV5UiDjQAbjY/3omUYIuFYEd5aQZYPZdDmZgC BnZSP8RSjKctfM/rJhuNUdAcROc10Q9YF0IQU7BqvBgHSyYS/nYQY/l2y 3Q9ghe4I2KPMtqg2KIXzmUQ/OnpDgVLZM3XZrDRgz+2QKyd20i5cXbyBL U=; X-IronPort-AV: E=Sophos;i="5.53,283,1531785600"; d="scan'208";a="628066830" Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-2a-e7be2041.us-west-2.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 24 Aug 2018 19:46:39 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-e7be2041.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7OJigM2128598 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 24 Aug 2018 19:44:43 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7OJigkU020019; Fri, 24 Aug 2018 15:44:42 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7OJig9t020017; Fri, 24 Aug 2018 15:44:42 -0400 To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 15:44:06 -0400 Message-Id: X-Mailer: git-send-email 2.18.0 In-Reply-To: References: Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.184.29 X-Mailman-Approved-At: Fri, 24 Aug 2018 16:47:11 -0400 Subject: [Qemu-devel] [PATCH 5/7] target/mips: Add MXU instruction D16MAC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Craig Janeczek via Qemu-devel From: "Denis V. Lunev\" via" Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adds support for emulating the D16MAC instruction. Signed-off-by: Craig Janeczek --- target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 64fc6089bb..221076711d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -366,6 +366,7 @@ enum { OPC_DCLO = 0x25 | OPC_SPECIAL2, /* MXU */ OPC_MXU_D16MUL = 0x08 | OPC_SPECIAL2, + OPC_MXU_D16MAC = 0x0A | OPC_SPECIAL2, OPC_MXU_S8LDD = 0x22 | OPC_SPECIAL2, OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2, OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2, @@ -3806,6 +3807,17 @@ typedef union { uint32_t sel:2; uint32_t special2:6; } D16MUL; + + struct { + uint32_t op:6; + uint32_t xra:4; + uint32_t xrb:4; + uint32_t xrc:4; + uint32_t xrd:4; + uint32_t optn2:2; + uint32_t aptn2:2; + uint32_t special2:6; + } D16MAC; } MXU_OPCODE; /* MXU Instructions */ @@ -3932,6 +3944,59 @@ static void gen_mxu(DisasContext *ctx, uint32_t opc) gen_store_mxu_gpr(t3, opcode->D16MUL.xra); gen_store_mxu_gpr(t2, opcode->D16MUL.xrd); break; + + case OPC_MXU_D16MAC: + gen_load_mxu_gpr(t1, opcode->D16MAC.xrb); + tcg_gen_ext16s_tl(t0, t1); + tcg_gen_shri_tl(t1, t1, 16); + tcg_gen_ext16s_tl(t1, t1); + gen_load_mxu_gpr(t3, opcode->D16MAC.xrc); + tcg_gen_ext16s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 16); + tcg_gen_ext16s_tl(t3, t3); + + switch (opcode->D16MAC.optn2) { + case 0: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 1: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case 2: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case 3: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, opcode->D16MAC.xra); + gen_load_mxu_gpr(t1, opcode->D16MAC.xrd); + + switch (opcode->D16MAC.aptn2) { + case 0: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case 1: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case 2: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case 3: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, opcode->D16MAC.xra); + gen_store_mxu_gpr(t2, opcode->D16MAC.xrd); + break; } tcg_temp_free(t0); @@ -18028,6 +18093,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU_S32M2I: case OPC_MXU_S8LDD: case OPC_MXU_D16MUL: + case OPC_MXU_D16MAC: gen_mxu(ctx, op1); break;