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Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR02MB1329 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe49::604 Subject: [Qemu-devel] [PATCH v5 6/9] xlnx-zynqmp-pmu: Connect the PMU interrupt controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, qemu-arm@nongnu.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/microblaze/xlnx-zynqmp-pmu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.14.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c index c6a0b3b8a1..828eeedc9f 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -24,6 +24,8 @@ #include "cpu.h" #include "boot.h" +#include "hw/intc/xlnx-pmu-iomod-intc.h" + /* Define the PMU device */ #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc" @@ -34,14 +36,18 @@ #define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000 #define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000 +#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000 + typedef struct XlnxZynqMPPMUSoCState { /*< private >*/ DeviceState parent_obj; /*< public >*/ MicroBlazeCPU cpu; + XlnxPMUIOIntc intc; } XlnxZynqMPPMUSoCState; + static void xlnx_zynqmp_pmu_soc_init(Object *obj) { XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj); @@ -50,6 +56,9 @@ static void xlnx_zynqmp_pmu_soc_init(Object *obj) TYPE_MICROBLAZE_CPU); object_property_add_child(obj, "pmu-cpu", OBJECT(&s->cpu), &error_abort); + + object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC); + qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default()); } static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) @@ -80,6 +89,21 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } + + object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size", + &error_abort); + object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge", + &error_abort); + object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive", + &error_abort); + object_property_set_bool(OBJECT(&s->intc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ)); } static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)