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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id m8-20020adfa3c8000000b0032d7fde2d3csm7990663wrb.79.2023.10.13.00.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:51:16 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org Cc: Emmanouil Pitsidianakis , "Michael S. Tsirkin" , Peter Xu , Jason Wang , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , David Woodhouse , Paul Durrant Subject: [RFC PATCH 42/78] hw/i386: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:47:51 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/i386/intel_iommu.c | 4 ++-- hw/i386/kvm/xen_evtchn.c | 2 +- hw/i386/x86.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2c832ab68b..bdb2ea3ac5 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2100,29 +2100,29 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s, /* Context-cache invalidation * Returns the Context Actual Invalidation Granularity. * @val: the content of the CCMD_REG */ static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val) { uint64_t caig; uint64_t type = val & VTD_CCMD_CIRG_MASK; switch (type) { case VTD_CCMD_DOMAIN_INVL: - /* Fall through */ + fallthrough; case VTD_CCMD_GLOBAL_INVL: caig = VTD_CCMD_GLOBAL_INVL_A; vtd_context_global_invalidate(s); break; case VTD_CCMD_DEVICE_INVL: caig = VTD_CCMD_DEVICE_INVL_A; vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val)); break; default: error_report_once("%s: invalid context: 0x%" PRIx64, __func__, val); caig = 0; } return caig; } @@ -2513,34 +2513,34 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) static bool vtd_process_context_cache_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { uint16_t sid, fmask; if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) { error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 " (reserved nonzero)", __func__, inv_desc->hi, inv_desc->lo); return false; } switch (inv_desc->lo & VTD_INV_DESC_CC_G) { case VTD_INV_DESC_CC_DOMAIN: trace_vtd_inv_desc_cc_domain( (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo)); - /* Fall through */ + fallthrough; case VTD_INV_DESC_CC_GLOBAL: vtd_context_global_invalidate(s); break; case VTD_INV_DESC_CC_DEVICE: sid = VTD_INV_DESC_CC_SID(inv_desc->lo); fmask = VTD_INV_DESC_CC_FM(inv_desc->lo); vtd_context_device_invalidate(s, sid, fmask); break; default: error_report_once("%s: invalid cc inv desc: hi=%"PRIx64", lo=%"PRIx64 " (invalid type)", __func__, inv_desc->hi, inv_desc->lo); return false; } return true; } diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index a731738411..d15e324f6e 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@ -2028,71 +2028,71 @@ static int find_be_port(XenEvtchnState *s, struct xenevtchn_handle *xc) int xen_be_evtchn_bind_interdomain(struct xenevtchn_handle *xc, uint32_t domid, evtchn_port_t guest_port) { XenEvtchnState *s = xen_evtchn_singleton; XenEvtchnPort *gp; uint16_t be_port = 0; int ret; if (!s) { return -ENOTSUP; } if (!xc) { return -EFAULT; } if (domid != xen_domid) { return -ESRCH; } if (!valid_port(guest_port)) { return -EINVAL; } qemu_mutex_lock(&s->port_lock); /* The guest has to have an unbound port waiting for us to bind */ gp = &s->port_table[guest_port]; switch (gp->type) { case EVTCHNSTAT_interdomain: /* Allow rebinding after migration, preserve port # if possible */ be_port = gp->type_val & ~PORT_INFO_TYPEVAL_REMOTE_QEMU; assert(be_port != 0); if (!s->be_handles[be_port]) { s->be_handles[be_port] = xc; xc->guest_port = guest_port; ret = xc->be_port = be_port; if (kvm_xen_has_cap(EVTCHN_SEND)) { assign_kernel_eventfd(gp->type, guest_port, xc->fd); } break; } - /* fall through */ + fallthrough; case EVTCHNSTAT_unbound: be_port = find_be_port(s, xc); if (!be_port) { ret = -ENOSPC; goto out; } gp->type = EVTCHNSTAT_interdomain; gp->type_val = be_port | PORT_INFO_TYPEVAL_REMOTE_QEMU; xc->guest_port = guest_port; if (kvm_xen_has_cap(EVTCHN_SEND)) { assign_kernel_eventfd(gp->type, guest_port, xc->fd); } ret = be_port; break; default: ret = -EINVAL; break; } out: qemu_mutex_unlock(&s->port_lock); return ret; } diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b3d054889b..c1fd0a966a 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -597,32 +597,32 @@ DeviceState *cpu_get_current_apic(void) void gsi_handler(void *opaque, int n, int level) { GSIState *s = opaque; trace_x86_gsi_interrupt(n, level); switch (n) { case 0 ... ISA_NUM_IRQS - 1: if (s->i8259_irq[n]) { /* Under KVM, Kernel will forward to both PIC and IOAPIC */ qemu_set_irq(s->i8259_irq[n], level); } - /* fall through */ + fallthrough; case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: #ifdef CONFIG_XEN_EMU /* * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC * routing actually works properly under Xen). And then to * *either* the PIRQ handling or the I/OAPIC depending on * whether the former wants it. */ if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { break; } #endif qemu_set_irq(s->ioapic_irq[n], level); break; case IO_APIC_SECONDARY_IRQBASE ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); break; } }