Message ID | cc1b3960a1a54125d2c87719fa945179bffbae68.1508329282.git.riku.voipio@linaro.org (mailing list archive) |
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State | New, archived |
Headers | show
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[91.157.170.157]) by smtp.gmail.com with ESMTPSA id j71sm2590718lfk.6.2017.10.18.05.33.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Oct 2017 05:33:36 -0700 (PDT) From: riku.voipio@linaro.org To: qemu-devel@nongnu.org Date: Wed, 18 Oct 2017 15:33:21 +0300 Message-Id: <cc1b3960a1a54125d2c87719fa945179bffbae68.1508329282.git.riku.voipio@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <cover.1508329282.git.riku.voipio@linaro.org> References: <cover.1508329282.git.riku.voipio@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PULL 07/10] linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Richard Henderson <rth@twiddle.net> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> X-Virus-Scanned: ClamAV using ClamSMTP |
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 79f85d3365..123f34783a 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -45,7 +45,11 @@ #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ #define TARGET_PHYS_ADDR_SPACE_BITS 32 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif #define SR_MD 30 #define SR_RB 29