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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id v10-20020a5d678a000000b0032d9f32b96csm569185wru.62.2023.10.13.01.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 01:50:48 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , Alistair Francis , Tyrone Ting , Hao Wu , Peter Maydell , qemu-arm@nongnu.org (open list:Nuvoton NPCM7xx) Subject: [RFC PATCH v3 72/78] hw/ssi: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 11:46:40 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/ssi/npcm7xx_fiu.c | 14 ++++++------- hw/ssi/omap_spi.c | 48 ++++++++++++++++++++++---------------------- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 4eedb2927e..fadd66a675 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -167,7 +167,7 @@ static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr, switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) { case FIU_ADDSIZ_4BYTES: ssi_transfer(fiu->spi, extract32(addr, 24, 8)); - /* fall through */ + fallthrough; case FIU_ADDSIZ_3BYTES: ssi_transfer(fiu->spi, extract32(addr, 16, 8)); ssi_transfer(fiu->spi, extract32(addr, 8, 8)); @@ -226,7 +226,7 @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v, switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) { case FIU_ADDSIZ_4BYTES: ssi_transfer(fiu->spi, extract32(addr, 24, 8)); - /* fall through */ + fallthrough; case FIU_ADDSIZ_3BYTES: ssi_transfer(fiu->spi, extract32(addr, 16, 8)); ssi_transfer(fiu->spi, extract32(addr, 8, 8)); @@ -285,16 +285,16 @@ static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr) switch (addsiz) { case 4: ssi_transfer(spi, extract32(addr, 24, 8)); - /* fall through */ + fallthrough; case 3: ssi_transfer(spi, extract32(addr, 16, 8)); - /* fall through */ + fallthrough; case 2: ssi_transfer(spi, extract32(addr, 8, 8)); - /* fall through */ + fallthrough; case 1: ssi_transfer(spi, extract32(addr, 0, 8)); - /* fall through */ + fallthrough; case 0: break; } @@ -391,7 +391,7 @@ static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v, value &= ~FIU_UMA_CFG_CMMLCK_MASK; value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK); } - /* fall through */ + fallthrough; case NPCM7XX_FIU_DRD_CFG: case NPCM7XX_FIU_DWR_CFG: if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) { diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c index 8f85c3e391..a0f367bd17 100644 --- a/hw/ssi/omap_spi.c +++ b/hw/ssi/omap_spi.c @@ -170,47 +170,47 @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size) return s->control; case 0x68: ch ++; - /* fall through */ + fallthrough; case 0x54: ch ++; - /* fall through */ + fallthrough; case 0x40: ch ++; - /* fall through */ + fallthrough; case 0x2c: /* MCSPI_CHCONF */ return s->ch[ch].config; case 0x6c: ch ++; - /* fall through */ + fallthrough; case 0x58: ch ++; - /* fall through */ + fallthrough; case 0x44: ch ++; - /* fall through */ + fallthrough; case 0x30: /* MCSPI_CHSTAT */ return s->ch[ch].status; case 0x70: ch ++; - /* fall through */ + fallthrough; case 0x5c: ch ++; - /* fall through */ + fallthrough; case 0x48: ch ++; - /* fall through */ + fallthrough; case 0x34: /* MCSPI_CHCTRL */ return s->ch[ch].control; case 0x74: ch ++; - /* fall through */ + fallthrough; case 0x60: ch ++; - /* fall through */ + fallthrough; case 0x4c: ch ++; - /* fall through */ + fallthrough; case 0x38: /* MCSPI_TX */ return s->ch[ch].tx; case 0x78: ch ++; - /* fall through */ + fallthrough; case 0x64: ch ++; - /* fall through */ + fallthrough; case 0x50: ch ++; - /* fall through */ + fallthrough; case 0x3c: /* MCSPI_RX */ s->ch[ch].status &= ~(1 << 0); /* RXS */ ret = s->ch[ch].rx; @@ -288,11 +288,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, break; case 0x68: ch ++; - /* fall through */ + fallthrough; case 0x54: ch ++; - /* fall through */ + fallthrough; case 0x40: ch ++; - /* fall through */ + fallthrough; case 0x2c: /* MCSPI_CHCONF */ if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ omap_mcspi_dmarequest_update(s->ch + ch); @@ -309,11 +309,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, break; case 0x70: ch ++; - /* fall through */ + fallthrough; case 0x5c: ch ++; - /* fall through */ + fallthrough; case 0x48: ch ++; - /* fall through */ + fallthrough; case 0x34: /* MCSPI_CHCTRL */ if (value & ~s->ch[ch].control & 1) { /* EN */ s->ch[ch].control |= 1; @@ -323,11 +323,11 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, break; case 0x74: ch ++; - /* fall through */ + fallthrough; case 0x60: ch ++; - /* fall through */ + fallthrough; case 0x4c: ch ++; - /* fall through */ + fallthrough; case 0x38: /* MCSPI_TX */ s->ch[ch].tx = value; s->ch[ch].status &= ~(1 << 1); /* TXS */