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[v1,19/21] m68k: correct typos

Message ID e24a3deefb9d721ace414719e8b773e6bf787fcf.1708419115.git.manos.pitsidianakis@linaro.org (mailing list archive)
State New, archived
Headers show
Series Trivial tree wide typo fixes | expand

Commit Message

Manos Pitsidianakis Feb. 20, 2024, 8:52 a.m. UTC
Correct typos automatically found with the `typos` tool
<https://crates.io/crates/typos>

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
---
 target/m68k/cpu.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Thomas Huth Feb. 20, 2024, 10:43 a.m. UTC | #1
On 20/02/2024 09.52, Manos Pitsidianakis wrote:
> Correct typos automatically found with the `typos` tool
> <https://crates.io/crates/typos>
> 
> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
> ---
>   target/m68k/cpu.h | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index aca4aa610b..57e3b6d3ce 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -478,10 +478,11 @@ void do_m68k_semihosting(CPUM68KState *env, int nr);
>    * The 68000 family is defined in six main CPU classes, the 680[012346]0.
>    * Generally each successive CPU adds enhanced data/stack/instructions.
>    * However, some features are only common to one, or a few classes.
> - * The features covers those subsets of instructons.
> + * The features covers those subsets of instructions.

While you're at it, please also remove the "s" from "covers".

  Thomas
diff mbox series

Patch

diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index aca4aa610b..57e3b6d3ce 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -478,10 +478,11 @@  void do_m68k_semihosting(CPUM68KState *env, int nr);
  * The 68000 family is defined in six main CPU classes, the 680[012346]0.
  * Generally each successive CPU adds enhanced data/stack/instructions.
  * However, some features are only common to one, or a few classes.
- * The features covers those subsets of instructons.
+ * The features covers those subsets of instructions.
  *
- * CPU32/32+ are basically 680010 compatible with some 68020 class instructons,
- * and some additional CPU32 instructions. Mostly Supervisor state differences.
+ * CPU32/32+ are basically 680010 compatible with some 68020 class
+ * instructions, and some additional CPU32 instructions. Mostly Supervisor
+ * state differences.
  *
  * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu.
  * There are 4 ColdFire core ISA revisions: A, A+, B and C.