From patchwork Mon Jul 31 13:09:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 9871833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7400660375 for ; Mon, 31 Jul 2017 13:11:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 531CA2856B for ; Mon, 31 Jul 2017 13:11:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 482F6285C2; Mon, 31 Jul 2017 13:11:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 77081285C4 for ; Mon, 31 Jul 2017 13:11:30 +0000 (UTC) Received: from localhost ([::1]:59500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcATO-00045x-5j for patchwork-qemu-devel@patchwork.kernel.org; Mon, 31 Jul 2017 09:11:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcASQ-00044v-Ar for qemu-devel@nongnu.org; Mon, 31 Jul 2017 09:10:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcASM-00035P-7C for qemu-devel@nongnu.org; Mon, 31 Jul 2017 09:10:02 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:57304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcASM-0002pJ-1O for qemu-devel@nongnu.org; Mon, 31 Jul 2017 09:09:58 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id BC7EEF0FD6A38; Mon, 31 Jul 2017 14:09:37 +0100 (IST) Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 31 Jul 2017 14:09:41 +0100 From: James Hogan To: Date: Mon, 31 Jul 2017 14:09:12 +0100 Message-ID: X-Mailer: git-send-email 2.13.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 1/2] mips: Improve segment defs for KVM T&E guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Paolo Bonzini , James Hogan , kvm@vger.kernel.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Improve the segment definitions used by get_physical_address() to yield target_ulong types, e.g. 0xffffffff80000000 instead of 0x80000000. This is in preparation for enabling emulation of MIPS KVM T&E segments in TCG MIPS targets, which unlike KVM could potentially have 64-bit target_ulong. In such a case the offset guest KSEG0 address ends up at e.g. 0x000000008xxxxxxx instead of 0xffffffff8xxxxxxx. This also allows the casts to int32_t that force sign extension to be removed, which removes any confusion due to relational comparison of unsigned (target_ulong) and signed (int32_t) types. Signed-off-by: James Hogan Cc: Yongbok Kim Cc: Aurelien Jarno Cc: Paolo Bonzini Cc: kvm@vger.kernel.org Reviewed-by: Philippe Mathieu-Daudé --- target/mips/helper.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index a2b79e8725a6..05883b9f4251 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -216,14 +216,14 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, /* effective address (modified for KVM T&E kernel segments) */ target_ulong address = real_address; -#define USEG_LIMIT 0x7FFFFFFFUL -#define KSEG0_BASE 0x80000000UL -#define KSEG1_BASE 0xA0000000UL -#define KSEG2_BASE 0xC0000000UL -#define KSEG3_BASE 0xE0000000UL +#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) +#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) +#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) +#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) +#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) -#define KVM_KSEG0_BASE 0x40000000UL -#define KVM_KSEG2_BASE 0x60000000UL +#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) +#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) if (kvm_enabled()) { /* KVM T&E adds guest kernel segments in useg */ @@ -307,17 +307,17 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, ret = TLBRET_BADADDR; } #endif - } else if (address < (int32_t)KSEG1_BASE) { + } else if (address < KSEG1_BASE) { /* kseg0 */ ret = get_segctl_physical_address(env, physical, prot, real_address, rw, access_type, mmu_idx, env->CP0_SegCtl1 >> 16, 0x1FFFFFFF); - } else if (address < (int32_t)KSEG2_BASE) { + } else if (address < KSEG2_BASE) { /* kseg1 */ ret = get_segctl_physical_address(env, physical, prot, real_address, rw, access_type, mmu_idx, env->CP0_SegCtl1, 0x1FFFFFFF); - } else if (address < (int32_t)KSEG3_BASE) { + } else if (address < KSEG3_BASE) { /* sseg (kseg2) */ ret = get_segctl_physical_address(env, physical, prot, real_address, rw, access_type, mmu_idx, @@ -974,8 +974,7 @@ void mips_cpu_do_interrupt(CPUState *cs) } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) && env->CP0_Config5 & (1 << CP0C5_CV))) { /* Force KSeg1 for cache errors */ - env->active_tc.PC = (int32_t)KSEG1_BASE | - (env->CP0_EBase & 0x1FFFF000); + env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000); } else { env->active_tc.PC = env->CP0_EBase & ~0xfff; }