From patchwork Fri Aug 24 19:44:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Denis V. Lunev\" via" X-Patchwork-Id: 10575895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A708920 for ; Fri, 24 Aug 2018 20:50:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A3D12CCF9 for ; Fri, 24 Aug 2018 20:50:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E36A2CCDB; Fri, 24 Aug 2018 20:50:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AAD062CCE3 for ; Fri, 24 Aug 2018 20:50:50 +0000 (UTC) Received: from localhost ([::1]:43599 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftJ2f-0002pu-V8 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 24 Aug 2018 16:50:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ftI57-0001Kx-7t for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:49:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ftI52-0007mk-VA for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:49:17 -0400 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:29927) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1ftI52-0007mI-MT for qemu-devel@nongnu.org; Fri, 24 Aug 2018 15:49:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1535140151; x=1566676151; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=g6gbt2Zq8OBgv7SbEU+RenuZ5lb1YTX43bmv3s42S50=; b=kDQQL4svI/odH5CVfA1jT2bl+Ipxm/lAP8UWULxv+/s+KjY7URqx81qj OnJE51rl4B9fdpH2he7Z5KRVTFfgSGbTbtvbrwE/ShwaZy2tjYKK09m4Q sltWuF+Gly5++acLI5XuGmZ7wgvuuj5f3o6tbnNqNfiE+DS1EYtcT3MKj 0=; X-IronPort-AV: E=Sophos;i="5.53,283,1531785600"; d="scan'208";a="628066833" Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-2b-c300ac87.us-west-2.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 24 Aug 2018 19:46:42 +0000 Received: from ua08cfde8192f59f8a244.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2b-c300ac87.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w7OJig5d092592 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 24 Aug 2018 19:44:43 GMT Received: from ua08cfde8192f59f8a244.ant.amazon.com (localhost [127.0.0.1]) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w7OJig6Z020006; Fri, 24 Aug 2018 15:44:42 -0400 Received: (from jancraig@localhost) by ua08cfde8192f59f8a244.ant.amazon.com (8.15.2/8.15.2/Submit) id w7OJig84020005; Fri, 24 Aug 2018 15:44:42 -0400 To: qemu-devel@nongnu.org Date: Fri, 24 Aug 2018 15:44:03 -0400 Message-Id: X-Mailer: git-send-email 2.18.0 In-Reply-To: References: Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 207.171.184.29 X-Mailman-Approved-At: Fri, 24 Aug 2018 16:47:11 -0400 Subject: [Qemu-devel] [PATCH 2/7] target/mips: Add MXU instructions S32I2M and S32M2I X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Craig Janeczek via Qemu-devel From: "Denis V. Lunev\" via" Reply-To: Craig Janeczek Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, Craig Janeczek Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Adds support for emulating the S32I2M and S32M2I MXU instructions. Signed-off-by: Craig Janeczek --- target/mips/translate.c | 55 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 50f0cb558f..381dfad36e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -364,6 +364,9 @@ enum { OPC_CLO = 0x21 | OPC_SPECIAL2, OPC_DCLZ = 0x24 | OPC_SPECIAL2, OPC_DCLO = 0x25 | OPC_SPECIAL2, + /* MXU */ + OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2, + OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2, /* Special */ OPC_SDBBP = 0x3F | OPC_SPECIAL2, }; @@ -3763,6 +3766,52 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, } } +typedef union { + struct { + uint32_t op:6; + uint32_t xra:5; + uint32_t:5; + uint32_t rb:5; + uint32_t:5; + uint32_t special2:6; + } S32I2M; + + struct { + uint32_t op:6; + uint32_t xra:5; + uint32_t:5; + uint32_t rb:5; + uint32_t:5; + uint32_t special2:6; + } S32M2I; +} MXU_OPCODE; + +/* MXU Instructions */ +static void gen_mxu(DisasContext *ctx, uint32_t opc) +{ +#ifndef TARGET_MIPS64 /* Only works in 32 bit mode */ + TCGv t0; + t0 = tcg_temp_new(); + MXU_OPCODE *opcode = (MXU_OPCODE *)&ctx->opcode; + + switch (opc) { + case OPC_MXU_S32I2M: + gen_load_gpr(t0, opcode->S32I2M.rb); + gen_store_mxu_gpr(t0, opcode->S32I2M.xra); + break; + + case OPC_MXU_S32M2I: + gen_load_mxu_gpr(t0, opcode->S32M2I.xra); + gen_store_gpr(t0, opcode->S32M2I.rb); + break; + } + + tcg_temp_free(t0); +#else + generate_exception_end(ctx, EXCP_RI); +#endif +} + /* Godson integer instructions */ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) @@ -17843,6 +17892,12 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, INSN_LOONGSON2F); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + + case OPC_MXU_S32I2M: + case OPC_MXU_S32M2I: + gen_mxu(ctx, op1); + break; + case OPC_CLO: case OPC_CLZ: check_insn(ctx, ISA_MIPS32);