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[3/7] target/openrisc: add numcores and coreid support

Message ID f8e2371c7a99cc6694b65d5be4f6c265dceae66a.1492384862.git.shorne@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Stafford Horne April 16, 2017, 11:23 p.m. UTC 
These are used to identify the processor in SMP system.  Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.

The proposal for this is available:
  https://openrisc.io/proposals/core-identifier-and-number-of-cores

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/sys_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Richard Henderson April 18, 2017, 8:01 a.m. UTC | #1 
On 04/16/2017 04:23 PM, Stafford Horne wrote:
> These are used to identify the processor in SMP system.  Their
> definition has been defined in verilog cores but it not yet part of the
> spec but it will be soon.
>
> The proposal for this is available:
>   https://openrisc.io/proposals/core-identifier-and-number-of-cores
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 2eaff87..bd5051b 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -227,6 +227,12 @@  target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 64): /* ESR */
         return env->esr;
 
+    case TO_SPR(0, 128): /* COREID */
+        return 0;
+
+    case TO_SPR(0, 129): /* NUMCORES */
+        return 1;
+
     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
         idx = spr - TO_SPR(1, 512);
         return env->tlb->dtlb[0][idx].mr;