From patchwork Sun Feb 26 11:07:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Usama Arif X-Patchwork-Id: 13152368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C428EC7EE31 for ; Sun, 26 Feb 2023 11:09:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229675AbjBZLJZ (ORCPT ); Sun, 26 Feb 2023 06:09:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229713AbjBZLJE (ORCPT ); Sun, 26 Feb 2023 06:09:04 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D05D8EB5A for ; Sun, 26 Feb 2023 03:08:13 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id bx12so277320wrb.11 for ; Sun, 26 Feb 2023 03:08:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=za/stY7P8yIh6gy9AN/5+S8qqKjzCyWV7DseUMDJu98=; b=eAVHKTnLEeB14Wc5pfNkSl1OrH8vejr5IQp1Q9N1Y4vZJFP0xp99Li2rnJCubHUJeQ ljStYlOADy9RtcDYg272MDzTvSN7sJK0ZQGd1YTZigBGB4akIv1g8QOiYsId5dKmVogC 2M+L0TdHIgkT+xtNpWN80XLz6OXE06FDk/2ma8WavWQjezPo785AJ5Uj33riYUxwknDt UaNvFteJ2GZfAR6qtH6+8BYTRvjDjvDgpdThPbfTjHQgRLsYaNUUneKoFKNPuPy7/G7S nKoG/Oq3vd1oB9snhdAV0EC5U0w/vYlXD2nSjG7D4/fluqjGdOJjyhs2dN8mh5gieV0M lMIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=za/stY7P8yIh6gy9AN/5+S8qqKjzCyWV7DseUMDJu98=; b=r5s0L73/b9DBCa5eR9pgyjG2tloeucZPyUq1e4HHCiRLpOMIDUGfJJdNzIcVV+CjCQ xwacuDAuLeBzlzEaQh1Psq7wtT2vAs//HbBr/1k93rpqY2dZOM7miQy2w8Z06YyeG7YW q7QeTg/3RD9JLZb8zRshEfMEydO863/YzivN20s3Kz79mbOGTLguB7iQTORjQ/oMZ+Rg hkjbm+1wy7Vb3NQ0XlMEAqmWtCRePC33pjMYB4SG1lHYmA01Vpi7kpkTckcE0zJ76eYN t2GOpTFq03kv5kcK5dlXFmc/vRCU7mZ+ov830AhcIiSERnXwbB6mQ87ixZuzc4kMlCDK 3Q+w== X-Gm-Message-State: AO0yUKV8CyO1MBImH8Xbrpfrm11l7r6qpUs5vMYvItPR3rDkgPDCLzsJ GTo+QeZ6tvOCISBHMDSVT33cKA== X-Google-Smtp-Source: AK7set+OEh1glJr1ki0yvrDdO0pAYmxGutVReznGFcjzHoJqqHbLX1g8+oMb8To83Ju+W/gdUtVRXA== X-Received: by 2002:adf:ea06:0:b0:2cb:3deb:c014 with SMTP id q6-20020adfea06000000b002cb3debc014mr430612wrm.28.1677409692009; Sun, 26 Feb 2023 03:08:12 -0800 (PST) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b566:0:df7b:4668:3e23:d0c9]) by smtp.gmail.com with ESMTPSA id v22-20020a1cf716000000b003e1fee8baacsm9157318wmh.25.2023.02.26.03.08.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 03:08:11 -0800 (PST) From: Usama Arif To: dwmw2@infradead.org, tglx@linutronix.de, kim.phillips@amd.com, brgerst@gmail.com Cc: piotrgorski@cachyos.org, oleksandr@natalenko.name, arjan@linux.intel.com, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, paulmck@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rcu@vger.kernel.org, mimoja@mimoja.de, hewenliang4@huawei.com, thomas.lendacky@amd.com, seanjc@google.com, pmenzel@molgen.mpg.de, fam.zheng@bytedance.com, punit.agrawal@bytedance.com, simon.evans@bytedance.com, liangma@liangbit.com, David Woodhouse , Usama Arif Subject: [PATCH v12 08/11] x86/smpboot: Remove initial_gs Date: Sun, 26 Feb 2023 11:07:59 +0000 Message-Id: <20230226110802.103134-9-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230226110802.103134-1-usama.arif@bytedance.com> References: <20230226110802.103134-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: rcu@vger.kernel.org From: Brian Gerst Use the percpu offset directly to set GSBASE. Signed-off-by: Brian Gerst Reviewed-by: David Woodhouse Signed-off-by: David Woodhouse Tested-by: Usama Arif Signed-off-by: Usama Arif Signed-off-by: David Woodhouse --- arch/x86/include/asm/realmode.h | 1 - arch/x86/kernel/acpi/sleep.c | 1 - arch/x86/kernel/head_64.S | 22 ++++++++-------------- arch/x86/kernel/smpboot.c | 2 -- 4 files changed, 8 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index a336feef0af1..f6a1737c77be 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -59,7 +59,6 @@ extern struct real_mode_header *real_mode_header; extern unsigned char real_mode_blob_end[]; extern unsigned long initial_code; -extern unsigned long initial_gs; extern unsigned long initial_stack; #ifdef CONFIG_AMD_MEM_ENCRYPT extern unsigned long initial_vc_handler; diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 236f2423454d..9d2d88424c77 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -112,7 +112,6 @@ int x86_acpi_suspend_lowlevel(void) #else /* CONFIG_64BIT */ #ifdef CONFIG_SMP current->thread.sp = (unsigned long)temp_stack + sizeof(temp_stack); - initial_gs = per_cpu_offset(smp_processor_id()); smpboot_control = smp_processor_id(); #endif initial_code = (unsigned long)wakeup_long64; diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 0ccca297e90e..069191e33490 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -66,18 +66,10 @@ SYM_CODE_START_NOALIGN(startup_64) leaq _text(%rip), %rdi - /* - * initial_gs points to initial fixed_percpu_data struct with storage for - * the stack protector canary. Global pointer fixups are needed at this - * stage, so apply them as is done in fixup_pointer(), and initialize %gs - * such that the canary can be accessed at %gs:40 for subsequent C calls. - */ + /* Setup GSBASE to allow stack canary access for C code */ movl $MSR_GS_BASE, %ecx - movq initial_gs(%rip), %rax - movq $_text, %rdx - subq %rdx, %rax - addq %rdi, %rax - movq %rax, %rdx + leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx + movl %edx, %eax shrq $32, %rdx wrmsr @@ -294,8 +286,11 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) * the per cpu areas are set up. */ movl $MSR_GS_BASE,%ecx - movl initial_gs(%rip),%eax - movl initial_gs+4(%rip),%edx +#ifndef CONFIG_SMP + leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx +#endif + movl %edx, %eax + shrq $32, %rdx wrmsr /* Setup and Load IDT */ @@ -437,7 +432,6 @@ SYM_CODE_END(vc_boot_ghcb) __REFDATA .balign 8 SYM_DATA(initial_code, .quad x86_64_start_kernel) -SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) #ifdef CONFIG_AMD_MEM_ENCRYPT SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) #endif diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index a22460a07cf8..b04520085582 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1084,8 +1084,6 @@ int common_cpu_up(unsigned int cpu, struct task_struct *idle) #ifdef CONFIG_X86_32 /* Stack for startup_32 can be just as for start_secondary onwards */ per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); -#else - initial_gs = per_cpu_offset(cpu); #endif return 0; }