From patchwork Wed Jan 29 07:24:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar,Vadivel MuruganX" X-Patchwork-Id: 11355595 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B3A513A4 for ; Wed, 29 Jan 2020 07:25:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2196120708 for ; Wed, 29 Jan 2020 07:25:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726216AbgA2HZ2 (ORCPT ); Wed, 29 Jan 2020 02:25:28 -0500 Received: from mga07.intel.com ([134.134.136.100]:7883 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726037AbgA2HZ2 (ORCPT ); Wed, 29 Jan 2020 02:25:28 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jan 2020 23:25:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,376,1574150400"; d="scan'208";a="229536242" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga003.jf.intel.com with ESMTP; 28 Jan 2020 23:24:57 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, vigneshr@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: robh+dt@kernel.org, dan.carpenter@oracle.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, "Ramuthevar,Vadivel MuruganX" Subject: [PATCH v8 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Date: Wed, 29 Jan 2020 15:24:53 +0800 Message-Id: <20200129072455.35807-1-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add support for the Cadence QSPI controller. This controller is present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. This driver has been tested on the Intel LGM SoCs. This driver does not support generic SPI and also the implementation only supports spi-mem interface to replace the existing driver in mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR flash memory. Thanks Vignesh for the review, modify, test and confirm the patch which is based on spi-mem based cadence driver working on TI's platform. after few changes started working on Intel's platform as well. changes from v7: -- remove addr_buf kept like as original -- drop bus-num, chipselect variable -- add soc_selection varible to differetiate the features -- replace dev->ddev in dma function -- add seperate function to handle the 24bit slave device address translation for lgm soc -- correct sentence seems incomplete in Kconfig -- add cqspi->soc_selection check to keep the original TI platform working code. changes from v6: -- Add the Signed-off-by Vignesh in commit message -- bus_num, num_chipselect added to avoid the garbage bus number during the probe and spi_register. -- master mode bits updated -- address sequence is different from TI and Intel SoC Ip handling so modified as per Intel and differentiating by use_dac_mode variable. -- dummy cycles also different b/w two platforms, so keeping separate check -- checkpatch errors which are intentional left as is for better readability changes from v5: -- kbuild test robot warnings fixed -- Add Reported-By: Dan Carpenter changes from v4: -- kbuild test robot warnings fixed -- Add Reborted-by: tag changes from v3: spi-cadence-quadspi.c -- static to all functions wrt to local to the file. -- Prefix cqspi_ and make the function static -- cmd_ops, data_ops and dummy_ops dropped -- addr_ops kept since it is required for address calculation. -- devm_ used for supported functions , removed legacy API's -- removed "indirect" name from functions -- replaced by master->mode_bits = SPI_RX_QUAD | SPI_TX_DUAL | SPI_RX_DUAL | SPI_RX_OCTAL; as per Vignesh susggestion -- removed free functions since devm_ handles automatically. -- dropped all unused Macros YAML file update: -- cadence,qspi.yaml file name replace by cdns,qspi-nor.yaml -- compatible string updated as per Vignesh suggestion -- for single entry, removed descriptions -- removed optional parameters Build Result: linux$ make DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml dt_binding_check CHKDT Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.yaml DTC Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dt.yaml CHECK Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dt.yaml Ramuthevar Vadivel Murugan (2): dt-bindings: spi: Add schema for Cadence QSPI Controller driver spi: cadence-quadpsi: Add support for the Cadence QSPI controller .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 147 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-cadence-quadspi.c | 1510 ++++++++++++++++++++ 4 files changed, 1667 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml create mode 100644 drivers/spi/spi-cadence-quadspi.c