Message ID | 20210716232504.182-1-a-nandan@ti.com (mailing list archive) |
---|---|
Headers | show |
Series | spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations | expand |
On Fri, 16 Jul 2021 23:25:01 +0000, Apurva Nandan wrote: > This series proposes fixes for cadence-quadspi controller for the > following issues with SPI NAND flashes: > > - Due to auto-HW polling without address phase, the cadence-quadspi > controller timeouts when performing any write operation on SPI NAND > flash. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [2/2] spi: cadence-quadspi: Fix check condition for DTR ops commit: 0395be967b067d99494113d78470574e86a02ed4 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark