[v2,0/5] Stacked/parallel memories bindings

Message

Miquel Raynal Nov. 26, 2021, 4:34 p.m. UTC

Hello Rob, Mark, Tudor & Pratyush,

Now that the discussion has move forward, let met propose a second
version for these bindings.

Cheers,
Miquèl

Changes in v2:
* Dropped the dtc changes for now.
* Moved the properties in the device's nodes, not the controller's.
* Dropped the useless #address-cells change.
* Added a missing "minItems".
* Moved the new properties in the spi-controller.yaml file.
* Added an example using two stacked memories in the
  spi-controller.yaml file.
* Renamed the properties to drop the Xilinx prefix.
* Added a patch to fix the spi-nor jedec yaml file.

Miquel Raynal (5):
  spi: dt-bindings: Allow describing flashes with two CS
  dt-bindings: mtd: spi-nor: Allow external properties
  dt-bindings: mtd: spi-nor: Allow two CS per device
  spi: dt-bindings: Describe stacked/parallel memories modes
  spi: dt-bindings: Add an example with two stacked flashes

 .../bindings/mtd/jedec,spi-nor.yaml           |  5 ++--
 .../bindings/spi/spi-controller.yaml          | 30 ++++++++++++++++++-
 2 files changed, 32 insertions(+), 3 deletions(-)