[v2,00/17] Update the Icicle Kit device tree

Message

Conor Dooley Dec. 17, 2021, 9:33 a.m. UTC

From: Conor Dooley <[e-mail]>

This series updates the Microchip Icicle Kit device tree by adding a
host of peripherals, and some updates to the memory map. In addition,
the device tree has been split into a third part, which contains "soft"
peripherals that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their
drivers upstreamed, so in those cases the dt bindings are included where
appropriate in order to avoid as many "DT compatible string <x> appears
un-documented" errors as possible.

Depends on mpfs clock driver series [1] to provide:
dt-bindings/clock/microchip,mpfs-clock.h
and on the other changes to the icicle/mpfs device tree (mmc) that are
already in linux/riscv/for-next.

Also depends on Geert's format changes to interrupt grouping etc [2].

Additionally, the interrupt-extended warnings on the plic/clint are 
cleared by [3] & [4], which lore appears to have been very confused about.

[1] https://lore.kernel.org/linux-clk/[e-mail]/T/
[2] https://lore.kernel.org/linux-riscv/[e-mail]/T/
[3] https://patchwork.kernel.org/project/linux-riscv/cover/[e-mail]/
[4] https://patchwork.kernel.org/project/linux-riscv/cover/[e-mail]/

Conor Dooley (16):
  dt-bindings: soc/microchip: update syscontroller compatibles
  dt-bindings: soc/microchip: make systemcontroller a mfd
  mailbox: change mailbox-mpfs compatible string
  dt-bindings: i2c: add bindings for microchip mpfs i2c
  dt-bindings: rng: add bindings for microchip mpfs rng
  dt-bindings: rtc: add bindings for microchip mpfs rtc
  dt-bindings: soc/microchip: add bindings for mpfs system services
  dt-bindings: gpio: add bindings for microchip mpfs gpio
  dt-bindings: spi: add bindings for microchip mpfs spi
  dt-bindings: usb: add bindings for microchip mpfs musb
  dt-bindings: pwm: add microchip corePWM binding
  riscv: dts: microchip: use hart and clk defines for icicle kit
  riscv: dts: microchip: add fpga fabric section to icicle kit
  riscv: dts: microchip: refactor icicle kit device tree
  riscv: dts: microchip: update peripherals in icicle kit device tree
  MAINTAINERS: update riscv/microchip entry

Ivan Griffin (1):
  dt-bindings: interrupt-controller: create a header for RISC-V
    interrupts

 .../bindings/gpio/microchip,mpfs-gpio.yaml    |  80 +++++
 .../bindings/i2c/microchip,mpfs-i2c.yaml      |  54 ++++
 ...ilbox.yaml => microchip,mpfs-mailbox.yaml} |   6 +-
 .../bindings/pwm/microchip,corepwm.yaml       |  61 ++++
 .../bindings/rng/microchip,mpfs-rng.yaml      |  29 ++
 .../bindings/rtc/microchip,mfps-rtc.yaml      |  63 ++++
 .../microchip,mpfs-generic-service.yaml       |  33 ++
 .../microchip,mpfs-sys-controller.yaml        |  62 ++++
 ...icrochip,polarfire-soc-sys-controller.yaml |  35 ---
 .../bindings/spi/microchip,mpfs-spi.yaml      |  61 ++++
 .../bindings/usb/microchip,mpfs-musb.yaml     |  61 ++++
 MAINTAINERS                                   |   2 +
 .../dts/microchip/microchip-mpfs-fabric.dtsi  |  13 +
 .../microchip/microchip-mpfs-icicle-kit.dts   | 111 +++++--
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 295 ++++++++++++++----
 drivers/mailbox/mailbox-mpfs.c                |   2 +-
 .../interrupt-controller/riscv-hart.h         |  19 ++
 17 files changed, 872 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
 create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
 rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
 create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
 create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
 create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
 delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
 create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
 create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
 create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
 create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h

Comments

Geert Uytterhoeven Dec. 17, 2021, 9:48 a.m. UTC | #1

Hi Conor,

On Fri, Dec 17, 2021 at 10:31 AM <[e-mail]> wrote:
> Also depends on Geert's format changes to interrupt grouping etc [2].
>
> Additionally, the interrupt-extended warnings on the plic/clint are
> cleared by [3] & [4], which lore appears to have been very confused about.

Right, it ended up being even more messier than I thought, and confuses
"b4 am" too.
I will resend these 3 series later today.

> [1] https://lore.kernel.org/linux-clk/[e-mail]/T/
> [2] https://lore.kernel.org/linux-riscv/[e-mail]/T/
> [3] https://patchwork.kernel.org/project/linux-riscv/cover/[e-mail]/
> [4] https://patchwork.kernel.org/project/linux-riscv/cover/[e-mail]/

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds