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Tue, 7 Jun 2022 11:47:08 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 7 Jun 2022 04:47:06 -0700 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 7 Jun 2022 04:47:03 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , "Krishna Yarlagadda" Subject: [Patch V3 0/3] spi: tegra quad: Add Tegra Grace features Date: Tue, 7 Jun 2022 17:16:56 +0530 Message-ID: <20220607114659.54314-1-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cdc0e2da-173f-463b-325c-08da487b73c8 X-MS-TrafficTypeDiagnostic: BYAPR12MB3415:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2022 11:47:08.6086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdc0e2da-173f-463b-325c-08da487b73c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3415 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add multiple chip select lines supported on Tegra 241 Changes in v3: Handle review comments. Move controller's properties to "nvidia,tegra210-quad.yaml". Fix style errors in peripheral yaml doc. Changes in v2: Split Wait polling changes to be handled later Change chip name to convention followed (Grace to 241) Add tegra qspi peripherals yaml file Krishna Yarlagadda (3): spi: tegra210-quad: Multi-cs support spi: dt-bindings: split peripheral prods spi: dt-bindings: Add compatible for Tegra241 QSPI ...nvidia,tegra210-quad-peripheral-props.yaml | 33 +++++++++++++++++++ .../bindings/spi/nvidia,tegra210-quad.yaml | 22 +------------ .../bindings/spi/spi-peripheral-props.yaml | 1 + drivers/spi/spi-tegra210-quad.c | 33 +++++++++++++++++-- 4 files changed, 66 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml