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Fri, 24 Feb 2023 07:49:48 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 24 Feb 2023 07:49:48 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 24 Feb 2023 07:49:43 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [Patch V4 0/3] Tegra TPM driver with HW flow control Date: Fri, 24 Feb 2023 21:19:38 +0530 Message-ID: <20230224154941.68587-1-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E8:EE_|MN0PR12MB6223:EE_ X-MS-Office365-Filtering-Correlation-Id: 71a77a00-5897-4a72-d16b-08db167ecf17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2023 15:50:09.7160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71a77a00-5897-4a72-d16b-08db167ecf17 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6223 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org TPM interface spec defines flow control where TPM device would drive MISO at same cycle as last address bit sent by controller on MOSI. This state of wait can be detected by software reading the MISO line or by controller hardware. Support sending transfers to controller in single message and handle flow control in hardware. Half duplex controllers have to support flow control in hardware. Tegra234 and Tegra241 chips have QSPI controller that supports TPM Interface Specification (TIS) flow control. Since the controller only supports half duplex, SW wait polling (flow control using full duplex transfers) method implemented in tpm_tis_spi_main.c will not work and have to us HW flow control. Updates in this patchset - Tegra QSPI identifies itself as half duplex. - TPM TIS SPI driver skips flow control for half duplex and send transfers in single message for controller to handle it. - TPM device identifies as TPM device for controller to detect and enable HW TPM wait poll feature. Verified with a TPM device on Tegra241 ref board using TPM2 tools. V4: - split api change to different patch - describe TPM HW flow control V3: - Use SPI device mode flag and SPI controller flags. - Drop usage of device tree flags. - Generic TPM half duplex controller handling. - HW & SW flow control for TPM. Drop additional driver. V2: - Fix dt schema errors. Krishna Yarlagadda (3): spi: Add TPM HW flow flag tpm_tis-spi: Support hardware wait polling spi: tegra210-quad: set half duplex flag drivers/char/tpm/tpm_tis_spi_main.c | 96 ++++++++++++++++++++++++++++- drivers/spi/spi-tegra210-quad.c | 1 + include/linux/spi/spi.h | 7 ++- 3 files changed, 99 insertions(+), 5 deletions(-)