From patchwork Wed Jul 24 14:00:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 13740996 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0806DDC5 for ; Wed, 24 Jul 2024 14:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721830124; cv=none; b=fo1UvAsiqdacUbO3FX8gjDNbR6cnJX05FECceIv9A3v8U7c4aBdEmVfSg68aWYnS0NTcTjfkCC7s1q/3GftFHHc2kWlN+GGOKFlfBqxWfhq8t90zOo0zf/buF/4D9zitRgsdkJ0gi5+81hyhP8MtqXUJV8YB5Sk5dE0LGF8QhJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721830124; c=relaxed/simple; bh=MZvKtfzKj4MfMbrdFSiHyC+ozLqJHzuOUwe6Slnko58=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=P2zrzrP5VDByFjxAVrtljHRwt/z918VnPOtWP76haVxYi/P8h+sPTFF2tukVEbgef7HVqjbY+Bp+iDj0kCpuY7zNVSXV9sfs/1AjuZs7OLpjYNTJT3tJTT++PoD9NQcIiBNmhg0/n7oBRIMDh/SpTk7kTwR0rv+GnJd3K67Jpu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RqmyqcwI; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RqmyqcwI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721830123; x=1753366123; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MZvKtfzKj4MfMbrdFSiHyC+ozLqJHzuOUwe6Slnko58=; b=RqmyqcwIvwUi4NkmaI4ll8egkPH8rahsxUL1/gqF2aX6j7LiD9LwN3G4 w/ZJspUp7m8jxs88WMGQgd55DHSa2a4oVfdvUhN7xxHdfCwKHKGCqxlAU 0XEE5fn1fhws4tNuYMN4CWxKL5Az69u6hy7uvrXfhlELEN5Ksz2fa2opd tw91FuC0kUyThDAai9OFlStSWG0oSFw/nRRwJm5uG6tuaZnbZrr6jm1WA ebfiZwd9WbrZsbttvsRSAy+kr0VZVYYnceQtQpqs2cWRZWCVEXy82Qu21 b2OhrBTjaGWi2kDiDBY1RgOUa6OGxfFMoWPYs9ra3RA0x5QlRU3Q8aGsY A==; X-CSE-ConnectionGUID: jx+4bigSRqamKB7xvH1mBg== X-CSE-MsgGUID: mMIDS+d9RsK775kKGtJh5g== X-IronPort-AV: E=McAfee;i="6700,10204,11143"; a="30173670" X-IronPort-AV: E=Sophos;i="6.09,233,1716274800"; d="scan'208";a="30173670" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2024 07:08:42 -0700 X-CSE-ConnectionGUID: Yu54/iKURGCDlHIIpcoDhQ== X-CSE-MsgGUID: PZhTCsgGStONePVwivoC5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,233,1716274800"; d="scan'208";a="83211315" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2024 07:08:38 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v2 00/12] spi: add driver for Intel discrete graphics Date: Wed, 24 Jul 2024 17:00:02 +0300 Message-Id: <20240724140014.428991-1-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add driver for access to Intel discrete graphics card internal SPI device. Expose device on auxiliary bus by i915 and Xe drivers and provide spi driver to register this device with MTD framework. This is a rewrite of "drm/i915/spi: spi access for discrete graphics" series with connection to the Xe driver and splitting the spi driver part to separate module in spi subsystem. V2: fix review comments fix signatures order depend spi presence in Xe on special flag, as not all new discrete cards have such spi Alexander Usyskin (6): spi: add driver for intel graphics on-die spi device spi: intel-dg: align 64bit read and write spi: intel-dg: wake card on operations drm/i915/spi: add support for access mode drm/xe/spi: add on-die spi device drm/xe/spi: add support for access mode Tomas Winkler (6): spi: intel-dg: implement region enumeration spi: intel-dg: implement spi access functions spi: intel-dg: spi register with mtd spi: intel-dg: implement mtd access handlers drm/i915/spi: add spi device for discrete graphics drm/i915/spi: add intel_spi_region map MAINTAINERS | 7 + drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/i915_driver.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/spi/intel_spi.c | 97 +++ drivers/gpu/drm/i915/spi/intel_spi.h | 15 + drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 5 + drivers/gpu/drm/xe/xe_device.c | 3 + drivers/gpu/drm/xe/xe_device_types.h | 8 + drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +- drivers/gpu/drm/xe/xe_pci.c | 5 + drivers/gpu/drm/xe/xe_spi.c | 104 ++++ drivers/gpu/drm/xe/xe_spi.h | 15 + drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + drivers/spi/spi-intel-dg.c | 863 ++++++++++++++++++++++++++ include/linux/intel_dg_spi_aux.h | 27 + 19 files changed, 1178 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h create mode 100644 drivers/gpu/drm/xe/xe_spi.c create mode 100644 drivers/gpu/drm/xe/xe_spi.h create mode 100644 drivers/spi/spi-intel-dg.c create mode 100644 include/linux/intel_dg_spi_aux.h