| Message ID | 20240724154739.582367-1-wsadowski@marvell.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Marvell HW overlay support for Cadence xSPI | expand |
On Wed, 24 Jul 2024 08:47:30 -0700, Witold Sadowski wrote: > This patch series adds support for the second version of the Marvell > hardware overlay for the Cadence xSPI IP block. The overlay is a hardware > change made around the original xSPI block. It extends xSPI features with > clock configuration, interrupt masking, and full-duplex, variable-length SPI > operations. > > These functionalities allow the xSPI block to operate not only with memory > devices but also with simple SPI devices and TPM devices. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/9] spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI commit: 49f63e6a89e94a757ef86340ec531668d26ecc30 [2/9] spi: cadence: Add static PHY configuration in Marvell overlay commit: b0d06169a7153f78b5356ca9e15cd836e43408dd [3/9] spi: cadence: Add clock configuration for Marvell xSPI overlay commit: 26d34fdc49712ddbd42b11102f5d9d78a0f42097 [4/9] spi: cadence: Add Marvell SDMA operations commit: 75128e2a14a9f443e8debdd30445f5934b5a7c83 [5/9] spi: cadence: Add Marvell xSPI interrupt changes commit: fa7279acef673f17550202d662f592672be26247 [6/9] spi: cadence: Add Marvell xfer operation support commit: 931e389ded0f1411cbf07ad50074dc2bcd49e1a8 [7/9] spi: cadence: Change resource mapping commit: 4b8cb7dcd8acd7a05354f0b458aca02e4497f2a6 [8/9] spi: cadence: Change cs property reading. commit: 8232f1e2584ac1eadd3282b035c306ebde87d8b4 [9/9] spi: cadence: Try to read spi-tx/rx-bus width property using ACPI commit: 9cabf4a487cd4035844b4928881a314334f348fe All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
This patch series adds support for the second version of the Marvell hardware overlay for the Cadence xSPI IP block. The overlay is a hardware change made around the original xSPI block. It extends xSPI features with clock configuration, interrupt masking, and full-duplex, variable-length SPI operations. These functionalities allow the xSPI block to operate not only with memory devices but also with simple SPI devices and TPM devices. Example ACPI entry: Device (SPI0) { Name (_HID, "PRP0001") // ACPI_DT_NAMESPACE_HID Name (_UID, 0) Name (_DDN, "SPI controller 0") Name (_CCA, ONE) Method (_STA) {Return (0xF)} Name (_CRS, ResourceTemplate() { QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804000000000, // MinAddress 0x804000001037, // MaxAddress 0, // AddressTranslation 0x1038) // AddressLength QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804010000000, // MinAddress 0x804010000007, // MaxAddress 0, // AddressTranslation 0x8) // AddressLength QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804000002000, // MinAddress 0x804000004027, // MaxAddress 0, // AddressTranslation 0x2028) // AddressLength QWordMemory ( ResourceConsumer,// ResourceUsage PosDecode, // Decode MinFixed, // MinType MaxFixed, // MaxType NonCacheable, // MemType ReadWrite, // ReadWriteType 0, // AddressGranularity 0x804000008000, // MinAddress 0x804000008237, // MaxAddress 0, // AddressTranslation 0x238) // AddressLength Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) { 0x7A } }) Name (_DSD, Package() { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "compatible", "marvell,cn10-xspi-nor"}, Package () { "reg", 0x8040}, } }) } // SPI0 Changes: v11: Fix SDMA x86 build issue. Instead of ioread64_rep use readq functions v10: Modify SDMA operation - Read as much data as possible using ioread64_rep, complete transfer with memcpy. Ignore first step if buffer is not alligned Clean unnecesary tennary operators Add spi_transfer_delay_exec call Rename "current_cycle_count" to "current_transfer_length" v9: Split into smaller patches: - Marvell overlay splitted into: PHY, Clock, Interrupt and SDMA ops - ACPI support splitted into resource mapping, CS parameter reading and tx/rx bus length Add separate ops and a few function pointers to distinguish between Cadence and Marvell: - SDMA read handler. - IRQ enable/disable handler - Separate mem_ops for Marvell xSPI Cleanup xfer code from magic numbers Add more descriptive commit msg for xfer block Use bitrev8 instead of custom bit reversal Rework Marvell SDMA read operations Add example ACPI entry v8: Rename xferbase to xfer Rework DLL reset, to return non inverted boolean value Rework STIG and SDMA status check, to return non inverted boolean value v7: Rebase patches to latest sources, changes in "Allow to read basic xSPI configuration from ACPI" Removed bugfix, as it was integrated to next tree from v6 v6: Fix item order in cdns,xspi.yaml v5: Rework cdns,xspi.yaml file Reword commit messages Move mamory mapping to ACPI patch Use devm_platform_ioremap_resource instead of two step mapping v4: Rename new Marvell registers to keep naming conventions Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor Various fixed for cdns,xspi.yaml file: - Remove unnecesary parameters - Link register xferbase with marvell,cn10-xspi-nor - Move default values to .c file from device-tree Clock configuration optimization ACPI fixes: - Remove incorrect ACPI match table Added .data field to device_id, fixes for matching in ACPI and dtb case Minor style comment changes v3: Removed all kconfig changes Added device-tree mrvl,xspi-nor tag v2: Support for second overlay iteration v1: - v0: Initial support for v1 overlay Witold Sadowski (9): spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI spi: cadence: Add static PHY configuration in Marvell overlay spi: cadence: Add clock configuration for Marvell xSPI overlay spi: cadence: Add Marvell SDMA operations spi: cadence: Add Marvell xSPI interrupt changes spi: cadence: Add Marvell xfer operation support spi: cadence: Change resource mapping spi: cadence: Change cs property reading. spi: cadence: Try to read spi-tx/rx-bus width property using ACPI .../devicetree/bindings/spi/cdns,xspi.yaml | 32 +- drivers/spi/spi-cadence-xspi.c | 692 +++++++++++++++++- 2 files changed, 704 insertions(+), 20 deletions(-)