| Message ID | 1360155984-15397-2-git-send-email-ezequiel.garcia@free-electrons.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Wed, Feb 06, 2013 at 10:06:21AM -0300, Ezequiel Garcia wrote: > The Armada 370 and Armada XP SoC has an SPI controller. > This patch adds support for this controller in Armada 370 > and Armada XP SoC common device tree files. > > Note that the Armada XP SPI register length is 0x50 bytes, > while Armada 370 SPI register length is 0x28 bytes, > so we choose the smaller of the two. > > Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Cc: Lior Amsalem <alior@marvell.com> > Acked-by: Gregory Clement <gregory.clement@free-electrons.com> > Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> > --- > Changes from v1: > * Register offset must be 0x28 instead of 0x50, > as pointed out by Gregory > > arch/arm/boot/dts/armada-370-xp.dtsi | 22 ++++++++++++++++++++++ > 1 files changed, 22 insertions(+), 0 deletions(-) Applied to mvebu/dt, resolved an add/add (i2c, mvsdio, usb) conflict. thx, Jason. ------------------------------------------------------------------------------ The Go Parallel Website, sponsored by Intel - in partnership with Geeknet, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials, tech docs, whitepapers, evaluation guides, and opinion stories. Check out the most recent posts - join the conversation now. http://goparallel.sourceforge.net/
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 4c0abe8..5cf8fb4 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -131,6 +131,28 @@ clocks = <&coreclk 0>; status = "disabled"; }; + + spi0: spi@d0010600 { + compatible = "marvell,orion-spi"; + reg = <0xd0010600 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@d0010680 { + compatible = "marvell,orion-spi"; + reg = <0xd0010680 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; };