From patchwork Wed Feb 5 13:05:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 3585911 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5533CC02DC for ; Wed, 5 Feb 2014 13:11:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 78812201B4 for ; Wed, 5 Feb 2014 13:11:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB73120170 for ; Wed, 5 Feb 2014 13:11:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751274AbaBENKH (ORCPT ); Wed, 5 Feb 2014 08:10:07 -0500 Received: from top.free-electrons.com ([176.31.233.9]:34388 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750775AbaBENKF (ORCPT ); Wed, 5 Feb 2014 08:10:05 -0500 Received: by mail.free-electrons.com (Postfix, from userid 106) id A21E5803; Wed, 5 Feb 2014 14:10:06 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id EFE287AC; Wed, 5 Feb 2014 14:10:05 +0100 (CET) From: Maxime Ripard To: Mark Brown , Mike Turquette , Emilio Lopez Cc: linux-sunxi@googlegroups.com, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kevin.z.m.zh@gmail.com, sunny@allwinnertech.com, shuge@allwinnertech.com, zhuzhenhua@allwinnertech.com, Maxime Ripard Subject: [PATCH v4 2/5] ARM: sun6i: dt: Add PLL6 and SPI module clocks Date: Wed, 5 Feb 2014 14:05:04 +0100 Message-Id: <1391605507-30981-3-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com> References: <1391605507-30981-1-git-send-email-maxime.ripard@free-electrons.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The module clocks in the A31 are still compatible with the A10 one. Add the SPI module clocks and the PLL6 in the device tree to allow their use by the SPI controllers. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 092bf97..93d7bb6 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -83,16 +83,12 @@ clocks = <&osc24M>; }; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - pll6: pll6 { + pll6: clk@01c20028 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6"; }; cpu: cpu@01c20050 { @@ -192,6 +188,38 @@ "apb2_uart1", "apb2_uart2", "apb2_uart3", "apb2_uart4", "apb2_uart5"; }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi2"; + }; + + spi3_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "spi3"; + }; }; soc@01c00000 {