From patchwork Mon Apr 28 03:53:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 4074911 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 880D8BFF02 for ; Mon, 28 Apr 2014 04:52:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 90D1A2020E for ; Mon, 28 Apr 2014 04:52:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D6262020A for ; Mon, 28 Apr 2014 04:52:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752402AbaD1Ewm (ORCPT ); Mon, 28 Apr 2014 00:52:42 -0400 Received: from mail-bn1lp0145.outbound.protection.outlook.com ([207.46.163.145]:52575 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751574AbaD1Ewl (ORCPT ); Mon, 28 Apr 2014 00:52:41 -0400 Received: from BY2PR03CA030.namprd03.prod.outlook.com (10.242.234.151) by BY2PR03MB427.namprd03.prod.outlook.com (10.141.141.146) with Microsoft SMTP Server (TLS) id 15.0.921.12; Mon, 28 Apr 2014 04:52:37 +0000 Received: from BL2FFO11FD026.protection.gbl (2a01:111:f400:7c09::114) by BY2PR03CA030.outlook.office365.com (2a01:111:e400:2c2c::23) with Microsoft SMTP Server (TLS) id 15.0.929.12 via Frontend Transport; Mon, 28 Apr 2014 04:52:30 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BL2FFO11FD026.mail.protection.outlook.com (10.173.161.105) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Mon, 28 Apr 2014 04:52:29 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3S4pr3d009014; Sun, 27 Apr 2014 21:52:26 -0700 From: Huang Shijie To: CC: , , , , , , , Huang Shijie Subject: [PATCH v2 09/10] mtd: spi-nor: add DDR quad read support for Micron Date: Mon, 28 Apr 2014 11:53:46 +0800 Message-ID: <1398657227-20721-10-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com> References: <1398657227-20721-1-git-send-email-b32955@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(199002)(189002)(99396002)(80976001)(46102001)(81542001)(87286001)(87936001)(81342001)(89996001)(93916002)(76176999)(575784001)(92726001)(74502001)(31966008)(77096999)(79102001)(4396001)(80022001)(6806004)(83072002)(83322001)(85852003)(77982001)(44976005)(92566001)(74662001)(48376002)(19580395003)(50226001)(19580405001)(50466002)(33646001)(77156001)(62966002)(88136002)(36756003)(47776003)(76482001)(20776003)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR03MB427; H:az84smr01.freescale.net; FPR:BF8EFECB.29C69D99.22D75BCF.48B99881.2022F; MLV:sfv; PTR:gate-az5.freescale.com; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01952C6E96 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the DDR(or DTR) quad read support for the Micron SPI NOR flash. Tested with n25q256a. Signed-off-by: Huang Shijie --- drivers/mtd/spi-nor/spi-nor.c | 5 +++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 07d249c..c5ea969 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -873,6 +873,9 @@ static int set_ddr_quad_mode(struct spi_nor *nor, u32 jedec_id) return status; } return status; + case CFI_MFR_ST: /* Micron, actually */ + /* DTR quad read works with the Extended SPI protocol. */ + return 0; default: return -EINVAL; } @@ -1072,6 +1075,8 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, case SPI_NOR_DDR_QUAD: if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) { /* Spansion */ nor->read_opcode = SPINOR_OP_READ_1_4_4_D; + } else if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { + nor->read_opcode = SPINOR_OP_READ_1_1_4_D; } else { dev_err(dev, "DDR Quad Read is not supported.\n"); return -EINVAL; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d191a6b..2fb40b6 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -27,6 +27,7 @@ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ +#define SPINOR_OP_READ_1_1_4_D 0x6d /* Read data bytes (DDR Quad SPI) */ #define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */