From patchwork Mon Apr 28 03:53:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 4075131 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A7B939F169 for ; Mon, 28 Apr 2014 05:07:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BFD132020A for ; Mon, 28 Apr 2014 05:07:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C5B6A20204 for ; Mon, 28 Apr 2014 05:07:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753245AbaD1FHy (ORCPT ); Mon, 28 Apr 2014 01:07:54 -0400 Received: from mail-by2lp0236.outbound.protection.outlook.com ([207.46.163.236]:21405 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753123AbaD1FHx (ORCPT ); Mon, 28 Apr 2014 01:07:53 -0400 Received: from BLUPR03CA033.namprd03.prod.outlook.com (10.141.30.26) by BLUPR03MB424.namprd03.prod.outlook.com (10.141.78.152) with Microsoft SMTP Server (TLS) id 15.0.929.12; Mon, 28 Apr 2014 04:52:21 +0000 Received: from BN1AFFO11FD007.protection.gbl (2a01:111:f400:7c10::139) by BLUPR03CA033.outlook.office365.com (2a01:111:e400:879::26) with Microsoft SMTP Server (TLS) id 15.0.934.12 via Frontend Transport; Mon, 28 Apr 2014 04:52:21 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BN1AFFO11FD007.mail.protection.outlook.com (10.58.52.67) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Mon, 28 Apr 2014 04:52:20 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3S4pr3a009014; Sun, 27 Apr 2014 21:52:17 -0700 From: Huang Shijie To: CC: , , , , , , , Huang Shijie Subject: [PATCH v2 06/10] mtd: fsl-quadspi: use the information stored in spi-nor{} Date: Mon, 28 Apr 2014 11:53:43 +0800 Message-ID: <1398657227-20721-7-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com> References: <1398657227-20721-1-git-send-email-b32955@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(199002)(189002)(377424004)(50226001)(81342001)(20776003)(85852003)(93916002)(76482001)(99396002)(81542001)(33646001)(48376002)(47776003)(77982001)(79102001)(89996001)(77156001)(36756003)(83072002)(31966008)(74662001)(46102001)(50466002)(74502001)(80022001)(87936001)(4396001)(62966002)(87286001)(80976001)(19580405001)(92566001)(88136002)(6806004)(44976005)(19580395003)(92726001)(83322001)(77096999)(76176999)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB424; H:az84smr01.freescale.net; FPR:B01E2443.AC3C2815.5DF85178.487A96B3.202C6; MLV:sfv; PTR:gate-az5.freescale.com; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01952C6E96 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can get the read/write/erase opcode from the spi nor framework now. What's more is that we can get the correct dummy cycles. This patch uses the information stored in the spi_nor{} to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Huang Shijie --- drivers/mtd/spi-nor/fsl-quadspi.c | 57 ++++++++++++------------------------ 1 files changed, 19 insertions(+), 38 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 8d659a2..4adf79e 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -280,8 +280,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) { void __iomem *base = q->iobase; int rxfifo = q->devtype_data->rxfifo; + struct spi_nor *nor = &q->nor[0]; + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; u32 lut_base; - u8 cmd, addrlen, dummy; + u8 op, dm; int i; fsl_qspi_unlock_lut(q); @@ -292,40 +294,28 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Quad Read */ lut_base = SEQID_QUAD_READ * 4; - - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR24BIT; - dummy = 8; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR32BIT; - dummy = 8; + op = nor->read_opcode; + dm = nor->read_dummy; + if (nor->flash_read == SPI_NOR_QUAD) { + if (op == SPINOR_OP_READ_1_1_4 || op == SPINOR_OP_READ4_1_1_4) { + /* read mode : 1-1-4 */ + writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + + writel(LUT0(DUMMY, PAD1, dm) | LUT1(READ, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } else { + dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op); + } } - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); - /* Write enable */ lut_base = SEQID_WREN * 4; writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); /* Page Program */ lut_base = SEQID_PP * 4; - - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_PP; - addrlen = ADDR24BIT; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_PP; - addrlen = ADDR32BIT; - } - - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + writel(LUT0(CMD, PAD1, nor->program_opcode) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); @@ -336,17 +326,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Erase a sector */ lut_base = SEQID_SE * 4; - - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_SE; - addrlen = ADDR24BIT; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_SE; - addrlen = ADDR32BIT; - } - - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + writel(LUT0(CMD, PAD1, nor->erase_opcode) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); /* Erase the whole chip */ @@ -396,6 +376,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) return SEQID_WRDI; case SPINOR_OP_RDSR: return SEQID_RDSR; + case SPINOR_OP_BE_4K: case SPINOR_OP_SE: return SEQID_SE; case SPINOR_OP_CHIP_ERASE: