diff mbox

[RFC,2/2] devicetree: Add devicetree bindings documentation for Zynq QSPI

Message ID 1404982207-4707-3-git-send-email-harinik@xilinx.com (mailing list archive)
State New, archived
Headers show

Commit Message

Harini Katakam July 10, 2014, 8:50 a.m. UTC 
Add bindings documentation for Zynq QSPI driver.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
---
 .../devicetree/bindings/spi/spi-zynq-qspi.txt      |   28 ++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
new file mode 100644
index 0000000..288c551
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
@@ -0,0 +1,28 @@ 
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "pclk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+- xlnx,qspi-mode	: Single - 0; Dual Stacked - 1; Dual Parallel - 2.
+
+Example:
+	qspi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "pclk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 19 4>;
+		num-cs = <1>;
+		xlnx,qspi-mode = <0x0>;
+		reg = <0xe000d000 0x1000>;
+	} ;