From patchwork Mon Sep 1 07:01:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Ungerer X-Patchwork-Id: 4817251 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 81690C0338 for ; Mon, 1 Sep 2014 07:19:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9D26F20108 for ; Mon, 1 Sep 2014 07:18:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6A393200F4 for ; Mon, 1 Sep 2014 07:18:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752738AbaIAHSK (ORCPT ); Mon, 1 Sep 2014 03:18:10 -0400 Received: from nskntqsrv03p.mx.bigpond.com ([61.9.168.237]:48600 "EHLO nskntqsrv03p.mx.bigpond.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752730AbaIAHSI (ORCPT ); Mon, 1 Sep 2014 03:18:08 -0400 X-Greylist: delayed 1007 seconds by postgrey-1.27 at vger.kernel.org; Mon, 01 Sep 2014 03:18:08 EDT Received: from nskntcmgw08p ([61.9.169.168]) by nskntmtas05p.mx.bigpond.com with ESMTP id <20140901070118.JOBZ19653.nskntmtas05p.mx.bigpond.com@nskntcmgw08p>; Mon, 1 Sep 2014 07:01:18 +0000 Received: from goober.accelecon.com ([149.135.16.88]) by nskntcmgw08p with BigPond Outbound id lj1H1o00P1u0AeD01j1HnG; Mon, 01 Sep 2014 07:01:18 +0000 X-Authority-Analysis: v=2.0 cv=D6DF24tj c=1 sm=1 a=tpHzvNDyw14p4wpd1xf5Bw==:17 a=grBK7dIYFHwA:10 a=Elh0ccRWDgYA:10 a=aFTPlZ8mLXYA:10 a=abLpnCq0AAAA:8 a=r3c5gKp63OnPD8yR_SMA:9 a=8itaGvuMXGQA:10 a=tpHzvNDyw14p4wpd1xf5Bw==:117 From: gerg@uclinux.org To: linux-spi@vger.kernel.org Cc: Greg Ungerer Subject: [PATCH] spi: orion: support armada extended baud rates Date: Mon, 1 Sep 2014 17:01:30 +1000 Message-Id: <1409554890-21239-1-git-send-email-gerg@uclinux.org> X-Mailer: git-send-email 1.9.1 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Greg Ungerer The Armada SoC family implementation of this SPI hardware module has extended the configuration register to allow for a wider range of SPI clock rates. Specifically the Serial Baud Rate Pre-selection bits in the SPI Interface Configuration Register now also use bits 6 and 7 as well. Modify the baud rate calculation to handle these differences for the Armada case. Potentially a baud rate can be setup using a number of different pre-scalar and scalar combinations. This code tries all possible pre-scalar divisors (8 in total) to try and find the most accuate set. Signed-off-by: Greg Ungerer --- drivers/spi/spi-orion.c | 77 +++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 61 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index c4675fa..816822f 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c @@ -40,6 +40,7 @@ #define ORION_SPI_MODE_CPHA (1 << 12) #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) #define ORION_SPI_CLK_PRESCALE_MASK 0x1F +#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ ORION_SPI_MODE_CPHA) @@ -82,31 +83,74 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) u32 rate; u32 prescale; u32 reg; + u32 mask; struct orion_spi *orion_spi; orion_spi = spi_master_get_devdata(spi->master); tclk_hz = clk_get_rate(orion_spi->clk); - /* - * the supported rates are: 4,6,8...30 - * round up as we look for equal or less speed - */ - rate = DIV_ROUND_UP(tclk_hz, speed); - rate = roundup(rate, 2); + if (of_machine_is_compatible("marvell,armada370")) { + unsigned int clk, spr, sppr, sppr2, err; + unsigned int best_spr, best_sppr, best_err; - /* check if requested speed is too small */ - if (rate > 30) - return -EINVAL; + best_err = speed; + best_spr = 0; + best_sppr = 0; - if (rate < 4) - rate = 4; + tclk_hz *= 10; + if (speed > tclk_hz) + return -EINVAL; - /* Convert the rate to SPI clock divisor value. */ - prescale = 0x10 + rate/2; + /* Iterate over the valid range looking for best fit */ + for (sppr = 0; sppr < 8; sppr++) { + sppr2 = 0x1 << sppr; + + spr = tclk_hz / sppr2; + spr = DIV_ROUND_UP(spr, speed); + if ((spr == 0) || (spr > 15)) + continue; + + clk = tclk_hz / (spr * sppr2); + err = speed - clk; + + if (err < best_err) { + best_spr = spr; + best_sppr = sppr; + best_err = err; + } + } + + if ((best_sppr == 0) && (best_spr == 0)) + return -EINVAL; + + prescale = ((best_sppr & 0x6) << 5) | + ((best_sppr & 0x1) << 4) | best_spr; + + mask = ARMADA_SPI_CLK_PRESCALE_MASK; + } else { + mask = ORION_SPI_CLK_PRESCALE_MASK; + + /* + * the supported rates are: 4,6,8...30 + * round up as we look for equal or less speed + */ + rate = DIV_ROUND_UP(tclk_hz, speed); + rate = roundup(rate, 2); + + /* check if requested speed is too small */ + if (rate > 30) + return -EINVAL; + + if (rate < 4) + rate = 4; + + /* Convert the rate to SPI clock divisor value. */ + prescale = 0x10 + rate/2; + } reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); - reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale); + reg = ((reg & ~mask) | prescale); writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); return 0; @@ -348,7 +392,7 @@ static int orion_spi_probe(struct platform_device *pdev) struct orion_spi *spi; struct resource *r; unsigned long tclk_hz; - int status = 0; + int mindiv, status = 0; master = spi_alloc_master(&pdev->dev, sizeof(*spi)); if (master == NULL) { @@ -390,7 +434,8 @@ static int orion_spi_probe(struct platform_device *pdev) tclk_hz = clk_get_rate(spi->clk); master->max_speed_hz = DIV_ROUND_UP(tclk_hz, 4); - master->min_speed_hz = DIV_ROUND_UP(tclk_hz, 30); + mindiv = (of_machine_is_compatible("marvell,armada370")) ? 1920 : 30; + master->min_speed_hz = DIV_ROUND_UP(tclk_hz, mindiv); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); spi->base = devm_ioremap_resource(&pdev->dev, r);