From patchwork Tue Sep 2 09:02:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barry Song X-Patchwork-Id: 4823731 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CF245C0338 for ; Tue, 2 Sep 2014 09:05:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 856A420170 for ; Tue, 2 Sep 2014 09:05:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CAC4F2018B for ; Tue, 2 Sep 2014 09:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752653AbaIBJF0 (ORCPT ); Tue, 2 Sep 2014 05:05:26 -0400 Received: from cluster-d.mailcontrol.com ([85.115.60.190]:38321 "EHLO cluster-d.mailcontrol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752524AbaIBJFZ (ORCPT ); Tue, 2 Sep 2014 05:05:25 -0400 Received: from shaapppus01.asia.root.pri ([210.13.83.99]) by rly04d.srv.mailcontrol.com (MailControl) with ESMTP id s8293Uxj027484 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Tue, 2 Sep 2014 10:03:41 +0100 Received: from SHAASIEXC01.ASIA.ROOT.PRI ([10.125.12.102]) by shaapppus01.asia.root.pri (PGP Universal service); Tue, 02 Sep 2014 17:03:42 +0800 X-PGP-Universal: processed; by shaapppus01.asia.root.pri on Tue, 02 Sep 2014 17:03:42 +0800 Received: from barry-laptop.ROOT.PRI (10.125.5.73) by asimail.csr.com (10.125.12.88) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 2 Sep 2014 17:03:29 +0800 From: Barry Song To: , CC: , , Qipan Li , Barry Song Subject: [PATCH 8/8] spi: sirf: make DMA transfer mode optional Date: Tue, 2 Sep 2014 17:02:37 +0800 Message-ID: <1409648557-5470-4-git-send-email-Barry.Song@csr.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1409648557-5470-1-git-send-email-Barry.Song@csr.com> References: <1409648557-5470-1-git-send-email-Barry.Song@csr.com> MIME-Version: 1.0 X-Originating-IP: [10.125.5.73] X-CFilter-Loop: Reflected X-Scanned-By: MailControl 33066.168 (www.mailcontrol.com) on 10.68.0.114 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Qipan Li some customers want a pure PIO transfer mode even though DMA mode is supported. here we give them a Kconfig option, but still keep the DMA enabled in default. Signed-off-by: Qipan Li Signed-off-by: Barry Song --- drivers/spi/Kconfig | 10 ++++++++++ drivers/spi/spi-sirf.c | 11 ++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 62e2242..0f84bd8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -477,6 +477,16 @@ config SPI_SIRF help SPI driver for CSR SiRFprimaII SoCs +config SPI_SIRF_DMA + bool "CSR SiRFprimaII/AtlasVI SPI DMA mode support" + depends on SPI_SIRF + default y + help + CSR SPI driver support DMA and PIO mode, select it let SPI driver support DMA mode + deselect it let SPI controller in PIO mode. + In CSR SPI driver distinguish the config to decide what transfer mode use. + Default configure value is y, if want pure PIO mode deselect it will be OK. + config SPI_SUN4I tristate "Allwinner A10 SoCs SPI controller" depends on ARCH_SUNXI || COMPILE_TEST diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c index 67d07b2..f934159 100644 --- a/drivers/spi/spi-sirf.c +++ b/drivers/spi/spi-sirf.c @@ -333,6 +333,7 @@ static void spi_sirfsoc_cmd_transfer(struct spi_device *spi, sspi->left_rx_word -= t->len; } +#ifdef CONFIG_SPI_SIRF_DMA static void spi_sirfsoc_dma_transfer(struct spi_device *spi, struct spi_transfer *t) { @@ -407,6 +408,7 @@ static void spi_sirfsoc_dma_transfer(struct spi_device *spi, if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX) writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); } +#endif static void spi_sirfsoc_pio_transfer(struct spi_device *spi, struct spi_transfer *t) @@ -474,8 +476,10 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) */ if (sspi->tx_by_cmd) spi_sirfsoc_cmd_transfer(spi, t); +#ifdef CONFIG_SPI_SIRF_DMA else if (IS_DMA_VALID(t)) spi_sirfsoc_dma_transfer(spi, t); +#endif else spi_sirfsoc_pio_transfer(spi, t); @@ -526,6 +530,11 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) u32 regval; u32 txfifo_ctrl, rxfifo_ctrl; u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4; +#ifdef CONFIG_SPI_SIRF_DMA + int spi_use_dma = 1; +#else + int spi_use_dma = 0; +#endif sspi = spi_master_get_devdata(spi->master); @@ -610,7 +619,7 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) regval |= SIRFSOC_SPI_CS_IO_MODE; writel(regval, sspi->base + SIRFSOC_SPI_CTRL); - if (IS_DMA_VALID(t)) { + if (spi_use_dma && IS_DMA_VALID(t)) { /* Enable DMA mode for RX, TX */ writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); writel(SIRFSOC_SPI_RX_DMA_FLUSH,