From patchwork Thu Jan 22 15:59:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 5686291 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 231989F358 for ; Thu, 22 Jan 2015 15:59:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7DC78202AE for ; Thu, 22 Jan 2015 15:59:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 93D4420160 for ; Thu, 22 Jan 2015 15:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752363AbbAVP7i (ORCPT ); Thu, 22 Jan 2015 10:59:38 -0500 Received: from mga03.intel.com ([134.134.136.65]:57339 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751396AbbAVP7i (ORCPT ); Thu, 22 Jan 2015 10:59:38 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 22 Jan 2015 07:55:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,449,1418112000"; d="scan'208";a="654961391" Received: from smile.fi.intel.com (HELO smile) ([10.237.72.90]) by fmsmga001.fm.intel.com with ESMTP; 22 Jan 2015 07:59:35 -0800 Received: from andy by smile with local (Exim 4.84) (envelope-from ) id 1YEKAR-0004iM-Q3; Thu, 22 Jan 2015 17:59:35 +0200 From: Andy Shevchenko To: Mark Brown , linux-spi@vger.kernel.org Cc: Andy Shevchenko Subject: [PATCH v1] spi: dw-mid: get a proper clock frequency for SPI2 Date: Thu, 22 Jan 2015 17:59:34 +0200 Message-Id: <1421942374-18083-1-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.1.4 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The clock information is being kept in the custom register on Intel MID platforms. Each controller has its own dedicated custom register for that. Thus, to get a proper frequency we have to read value from the specific offset to the register block. This patch makes this happen. Fixes: d58cf5ff6500 (spi: dw-pci: describe Intel MID controllers better) Signed-off-by: Andy Shevchenko --- Mark, this is material for 3.19-rcX since I introduced the SPI2 just in 3.19-rc1. drivers/spi/spi-dw-mid.c | 13 ++++++++----- drivers/spi/spi-dw-pci.c | 6 +++--- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index 47a8e65..a0197fd 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c @@ -247,9 +247,9 @@ static struct dw_spi_dma_ops mid_dma_ops = { /* Some specific info for SPI0 controller on Intel MID */ -/* HW info for MRST CLk Control Unit, one 32b reg */ +/* HW info for MRST Clk Control Unit, 32b reg per controller */ #define MRST_SPI_CLK_BASE 100000000 /* 100m */ -#define MRST_CLK_SPI0_REG 0xff11d86c +#define MRST_CLK_SPI_REG 0xff11d86c #define CLK_SPI_BDIV_OFFSET 0 #define CLK_SPI_BDIV_MASK 0x00000007 #define CLK_SPI_CDIV_OFFSET 9 @@ -261,13 +261,16 @@ int dw_spi_mid_init(struct dw_spi *dws) void __iomem *clk_reg; u32 clk_cdiv; - clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16); + clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16); if (!clk_reg) return -ENOMEM; - /* get SPI controller operating freq info */ - clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET; + /* Get SPI controller operating freq info */ + clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32)); + clk_cdiv &= CLK_SPI_CDIV_MASK; + clk_cdiv >>= CLK_SPI_CDIV_OFFSET; dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1); + iounmap(clk_reg); #ifdef CONFIG_SPI_DW_MID_DMA diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c index 64f3efa..5ba3310 100644 --- a/drivers/spi/spi-dw-pci.c +++ b/drivers/spi/spi-dw-pci.c @@ -82,14 +82,14 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) * clock rate, FIFO depth. */ if (desc) { + dws->num_cs = desc->num_cs; + dws->bus_num = desc->bus_num; + if (desc->setup) { ret = desc->setup(dws); if (ret) return ret; } - - dws->num_cs = desc->num_cs; - dws->bus_num = desc->bus_num; } else { return -ENODEV; }