| Message ID | 1424803388-6033-1-git-send-email-andriy.shevchenko@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2015-02-25 2:43 GMT+08:00 Andy Shevchenko <andriy.shevchenko@linux.intel.com>: > The commit d297933cc7fc (spi: dw: Fix detecting FIFO depth) tries to fix the > logic of the FIFO detection based on the description on the comments. However, > there is a slight difference between numbers in TX Level and TX FIFO size. > > So, by specification the FIFO size would be in a range 2-256 bytes. From TX > Level prospective it means we can set threshold in the range 0-(FIFO size - 1) > bytes. Hence there are currently two issues: > a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be > either 0 or 1 byte; > b) FIFO size is incorrectly decreased by 1 which already done by meaning of > TX Level register. > > This patch fixes it eventually right. > > Fixes: d297933cc7fc (spi: dw: Fix detecting FIFO depth) > Cc: Axel Lin <axel.lin@ingics.com> > Cc: stable@vger.kernel.org > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Axel Lin <axel.lin@ingics.com> -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
2015-02-25 2:43 GMT+08:00 Andy Shevchenko <andriy.shevchenko@linux.intel.com>: > The commit d297933cc7fc (spi: dw: Fix detecting FIFO depth) tries to fix the > logic of the FIFO detection based on the description on the comments. However, > there is a slight difference between numbers in TX Level and TX FIFO size. > > So, by specification the FIFO size would be in a range 2-256 bytes. From TX > Level prospective it means we can set threshold in the range 0-(FIFO size - 1) > bytes. Hence there are currently two issues: > a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be > either 0 or 1 byte; > b) FIFO size is incorrectly decreased by 1 which already done by meaning of > TX Level register. > > This patch fixes it eventually right. > > Fixes: d297933cc7fc (spi: dw: Fix detecting FIFO depth) > Cc: Axel Lin <axel.lin@ingics.com> > Cc: stable@vger.kernel.org > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > --- > > Shame on me I somehow missed this when tested mentioned patch. > > drivers/spi/spi-dw.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > index 0257dd1..ba9773d 100644 > --- a/drivers/spi/spi-dw.c > +++ b/drivers/spi/spi-dw.c > @@ -494,14 +494,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) > if (!dws->fifo_len) { > u32 fifo; > > - for (fifo = 2; fifo <= 256; fifo++) { > + for (fifo = 1; fifo <= 256; fifo++) { I think the upper bound of the for loop should be 255 (FIFO size - 1) for (fifo = 1; fifo <= 255; fifo++) { so if writting 255 to DW_SPI_TXFLTR success, fifo_len is 256. no need to test writing 256 to DW_SPI_TXFLTR. -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, 2015-02-25 at 12:53 +0800, Axel Lin wrote: > 2015-02-25 2:43 GMT+08:00 Andy Shevchenko <andriy.shevchenko@linux.intel.com>: > > The commit d297933cc7fc (spi: dw: Fix detecting FIFO depth) tries to fix the > > logic of the FIFO detection based on the description on the comments. However, > > there is a slight difference between numbers in TX Level and TX FIFO size. > > > > So, by specification the FIFO size would be in a range 2-256 bytes. From TX > > Level prospective it means we can set threshold in the range 0-(FIFO size - 1) > > bytes. Hence there are currently two issues: > > a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be > > either 0 or 1 byte; > > b) FIFO size is incorrectly decreased by 1 which already done by meaning of > > TX Level register. > > > > This patch fixes it eventually right. > > > > Fixes: d297933cc7fc (spi: dw: Fix detecting FIFO depth) > > Cc: Axel Lin <axel.lin@ingics.com> > > Cc: stable@vger.kernel.org > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > --- > > > > Shame on me I somehow missed this when tested mentioned patch. > > > > drivers/spi/spi-dw.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c > > index 0257dd1..ba9773d 100644 > > --- a/drivers/spi/spi-dw.c > > +++ b/drivers/spi/spi-dw.c > > @@ -494,14 +494,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) > > if (!dws->fifo_len) { > > u32 fifo; > > > > - for (fifo = 2; fifo <= 256; fifo++) { > > + for (fifo = 1; fifo <= 256; fifo++) { > > I think the upper bound of the for loop should be 255 (FIFO size - 1) > for (fifo = 1; fifo <= 255; fifo++) { > so if writting 255 to DW_SPI_TXFLTR success, fifo_len is 256. > > no need to test writing 256 to DW_SPI_TXFLTR. Yes, I even just retested carefully. I will change to < 256 and keep your Reviewed-by tag in v2, hope it's okay.
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 0257dd1..ba9773d 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -494,14 +494,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) if (!dws->fifo_len) { u32 fifo; - for (fifo = 2; fifo <= 256; fifo++) { + for (fifo = 1; fifo <= 256; fifo++) { dw_writew(dws, DW_SPI_TXFLTR, fifo); if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) break; } dw_writew(dws, DW_SPI_TXFLTR, 0); - dws->fifo_len = (fifo == 2) ? 0 : fifo - 1; + dws->fifo_len = (fifo == 1) ? 0 : fifo; dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); } }
The commit d297933cc7fc (spi: dw: Fix detecting FIFO depth) tries to fix the logic of the FIFO detection based on the description on the comments. However, there is a slight difference between numbers in TX Level and TX FIFO size. So, by specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. This patch fixes it eventually right. Fixes: d297933cc7fc (spi: dw: Fix detecting FIFO depth) Cc: Axel Lin <axel.lin@ingics.com> Cc: stable@vger.kernel.org Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- Shame on me I somehow missed this when tested mentioned patch. drivers/spi/spi-dw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)