From patchwork Mon Apr 6 21:29:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 6166091 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D41BC9F2EC for ; Mon, 6 Apr 2015 21:29:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E5B6B20379 for ; Mon, 6 Apr 2015 21:29:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E1E8020364 for ; Mon, 6 Apr 2015 21:29:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752928AbbDFV3L (ORCPT ); Mon, 6 Apr 2015 17:29:11 -0400 Received: from mail-qk0-f202.google.com ([209.85.220.202]:34140 "EHLO mail-qk0-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752687AbbDFV3K (ORCPT ); Mon, 6 Apr 2015 17:29:10 -0400 Received: by qkbw1 with SMTP id w1so7053599qkb.1 for ; Mon, 06 Apr 2015 14:29:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=0KECm/stuYBXHVmt3n3myd2L8I4mRN4LAQ+JHBaAuIs=; b=jxl1icJZ9HHlABY1JQvwyuXbmAqkUrLet+7Pm7usK1xuCXsxTqiggSAvdBo8ba0ogx lCB2cIa9mY3kPOkaDDFWvQusheankKsSj8GYVymEIhcpTiHELq8WlsbzuFy0x7C7m9GS h0z8ayWUslP26OuHqPjFHRpI5+YZgmBnncBGZuvDgsyFkQHaY5SmaW2MIokUxX+8ypmJ Gzg9glyLHnt87yqZT44quPwUaRVf1x/e4t8l+Ab81JbUbXrae6veUcioTaohnEkFu2/S mT8rZvxSYyuVpucB/ds2fQ96xkGqUPqAlxc/YwY3vwiFXnYl4+N1I6sW20+8EDazkDaW qylw== X-Gm-Message-State: ALoCoQlwt20ygDPu+AmQxywjw3Xx7SFXqu2po+e69J/DOROieIghxLoYGK7/uFvUJpCvZxHyV7MJ X-Received: by 10.140.234.150 with SMTP id f144mr15742212qhc.9.1428355749212; Mon, 06 Apr 2015 14:29:09 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id z21si247446yhc.5.2015.04.06.14.29.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Apr 2015 14:29:09 -0700 (PDT) Received: from abrestic.mtv.corp.google.com ([172.22.65.70]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id cK90LszT.1; Mon, 06 Apr 2015 14:29:09 -0700 Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 3CB31220BE9; Mon, 6 Apr 2015 14:29:08 -0700 (PDT) From: Andrew Bresticker To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH 1/5] spi: img-spfi: Limit bit clock to 1/4th of input clock Date: Mon, 6 Apr 2015 14:29:03 -0700 Message-Id: <1428355747-16822-1-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Although the SPFI BITCLK divider supports a value of up to 255, only values up to 128 are usable. This results in a maximum possible bit clock rate of 1/4th the input clock rate. Signed-off-by: Andrew Bresticker --- drivers/spi/spi-img-spfi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index e649bc7..7d18bec 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c @@ -405,10 +405,10 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi, /* * output = spfi_clk * (BITCLK / 512), where BITCLK must be a - * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits) + * power of 2 up to 128 */ - div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz); - div = clamp(512 / (1 << get_count_order(div)), 1, 255); + div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); + div = clamp(512 / (1 << get_count_order(div)), 1, 128); val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << @@ -594,8 +594,8 @@ static int img_spfi_probe(struct platform_device *pdev) master->num_chipselect = 5; master->dev.of_node = pdev->dev.of_node; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); - master->max_speed_hz = clk_get_rate(spfi->spfi_clk); - master->min_speed_hz = master->max_speed_hz / 512; + master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4; + master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512; master->set_cs = img_spfi_set_cs; master->transfer_one = img_spfi_transfer_one;