From patchwork Mon May 11 15:20:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 6378681 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1106A9F32B for ; Mon, 11 May 2015 15:23:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2F77A2076B for ; Mon, 11 May 2015 15:23:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0FAC420748 for ; Mon, 11 May 2015 15:23:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751184AbbEKPXu (ORCPT ); Mon, 11 May 2015 11:23:50 -0400 Received: from mail-wi0-f175.google.com ([209.85.212.175]:36318 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751208AbbEKPXu (ORCPT ); Mon, 11 May 2015 11:23:50 -0400 Received: by wizk4 with SMTP id k4so110192411wiz.1 for ; Mon, 11 May 2015 08:23:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2GVN//rrRruxYGY+XBdn8eu8wNPhnTCGfw26nwUXjsY=; b=SGTRZmr0qh0JNOrb//tyFUpb8iaMDXU7sxSxJKNgp9DQd6DCvToSUQmt8L77kIo22f evzRsioM8geE88tYIO+RS1v2fwNzqBvCSXbvWcnR2T0WmFLfpMk/oXJnPcuEDQsDm9Px V5JXeewF08cQsrLkj1T7JxGbJgbFDvGURm2hMxTNpRIKa25zOTOmUJBLtkyhVSF4qEIW Bvms+DFQV9k8I+/t9SSk9pE23sV3UrQYthxVxkJ48f8aiiUiXtN41HjE1yTXJCArYtYW EwcsFL7127Bare4lyGXGVeB0Dv2WWK37ILSIxSbOlF1KQCVW24srk3p03rGjed04Q+lB 2g0g== X-Gm-Message-State: ALoCoQluUpmh8ZGnwrsM7KsMfbow2v0Nr8PX316NAMcba63Dobt7az8MvAwohzOSyoML887z+fO+ X-Received: by 10.180.96.41 with SMTP id dp9mr20180861wib.77.1431357829276; Mon, 11 May 2015 08:23:49 -0700 (PDT) Received: from laptop.hh.imgtec.org ([190.2.108.156]) by mx.google.com with ESMTPSA id mv11sm246234wic.23.2015.05.11.08.23.46 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 May 2015 08:23:48 -0700 (PDT) From: Ezequiel Garcia To: Mark Brown , Linus Walleij Cc: , Ezequiel Garcia Subject: [PATCH] spi: pl022: Specify 'num-cs' property as required in devicetree binding Date: Mon, 11 May 2015 12:20:18 -0300 Message-Id: <1431357618-6829-1-git-send-email-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.3.3 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since commit 39a6ac11df65 ("spi/pl022: Devicetree support w/o platform data") the 'num-cs' parameter cannot be passed through platform data when probing with devicetree. Instead, it's a required devicetree property. Fix the binding documentation so the property is properly specified. Fixes: 39a6ac11df65 ("spi/pl022: Devicetree support w/o platform data") Signed-off-by: Ezequiel Garcia --- Documentation/devicetree/bindings/spi/spi_pl022.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt index 22ed679..4d1673c 100644 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -4,9 +4,9 @@ Required properties: - compatible : "arm,pl022", "arm,primecell" - reg : Offset and length of the register set for the device - interrupts : Should contain SPI controller interrupt +- num-cs : total number of chipselects Optional properties: -- num-cs : total number of chipselects - cs-gpios : should specify GPIOs used for chipselects. The gpios will be referred to as reg = in the SPI child nodes. If unspecified, a single SPI device without a chip select can be used.