From patchwork Wed Jun 3 10:49:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 6534011 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 93352C0020 for ; Wed, 3 Jun 2015 10:50:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 57DEC20690 for ; Wed, 3 Jun 2015 10:50:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3E34B20696 for ; Wed, 3 Jun 2015 10:50:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752291AbbFCKuA (ORCPT ); Wed, 3 Jun 2015 06:50:00 -0400 Received: from mga14.intel.com ([192.55.52.115]:26917 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752303AbbFCKuA (ORCPT ); Wed, 3 Jun 2015 06:50:00 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 03 Jun 2015 03:50:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,546,1427785200"; d="scan'208";a="502050784" Received: from mylly.fi.intel.com (HELO mylly.fi.intel.com.) ([10.237.72.55]) by FMSMGA003.fm.intel.com with ESMTP; 03 Jun 2015 03:49:58 -0700 From: Jarkko Nikula To: linux-spi@vger.kernel.org Cc: Mark Brown , Jarkko Nikula Subject: [PATCH 2/3] spi: pxa2xx: Prepare for new Intel LPSS SPI type Date: Wed, 3 Jun 2015 13:49:46 +0300 Message-Id: <1433328587-20797-2-git-send-email-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1433328587-20797-1-git-send-email-jarkko.nikula@linux.intel.com> References: <1433328587-20797-1-git-send-email-jarkko.nikula@linux.intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the Intel LPSS SPI properties will be different in upcoming platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI private registers will be at different offset and there will be changes in individual registers and default FIFO thresholds too. Add configuration for these differences and use them in runtime based on LPSS SSP type. With this change private registers offset autodetection becomes needless. Signed-off-by: Jarkko Nikula --- drivers/spi/spi-pxa2xx.c | 107 +++++++++++++++++++++++++-------------------- include/linux/pxa2xx_ssp.h | 2 +- 2 files changed, 60 insertions(+), 49 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 13ec36b1c9aa..174b88e44987 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -60,18 +60,51 @@ MODULE_ALIAS("platform:pxa2xx-spi"); | QUARK_X1000_SSCR1_TFT \ | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) -#define LPSS_RX_THRESH_DFLT 64 -#define LPSS_TX_LOTHRESH_DFLT 160 -#define LPSS_TX_HITHRESH_DFLT 224 - -/* Offset from drv_data->lpss_base */ -#define GENERAL_REG 0x08 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) -#define SSP_REG 0x0c -#define SPI_CS_CONTROL 0x18 #define SPI_CS_CONTROL_SW_MODE BIT(0) #define SPI_CS_CONTROL_CS_HIGH BIT(1) +struct lpss_config { + /* LPSS offset from drv_data->ioaddr */ + unsigned offset; + /* Register offsets from drv_data->lpss_base or -1 */ + int reg_general; + int reg_ssp; + int reg_cs_ctrl; + /* FIFO thresholds */ + u32 rx_threshold; + u32 tx_threshold_lo; + u32 tx_threshold_hi; +}; + +/* Keep these sorted with enum pxa_ssp_type */ +static const struct lpss_config lpss_platforms[] = { + { /* LPSS_LPT_SSP */ + .offset = 0x800, + .reg_general = 0x08, + .reg_ssp = 0x0c, + .reg_cs_ctrl = 0x18, + .rx_threshold = 64, + .tx_threshold_lo = 160, + .tx_threshold_hi = 224, + }, + { /* LPSS_BYT_SSP */ + .offset = 0x400, + .reg_general = 0x08, + .reg_ssp = 0x0c, + .reg_cs_ctrl = 0x18, + .rx_threshold = 64, + .tx_threshold_lo = 160, + .tx_threshold_hi = 224, + }, +}; + +static inline const struct lpss_config +*lpss_get_config(const struct driver_data *drv_data) +{ + return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; +} + static bool is_lpss_ssp(const struct driver_data *drv_data) { return drv_data->ssp_type == LPSS_LPT_SSP || @@ -193,63 +226,39 @@ static void __lpss_ssp_write_priv(struct driver_data *drv_data, */ static void lpss_ssp_setup(struct driver_data *drv_data) { - unsigned offset = 0x400; - u32 value, orig; - - /* - * Perform auto-detection of the LPSS SSP private registers. They - * can be either at 1k or 2k offset from the base address. - */ - orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); - - /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ - value = orig | SPI_CS_CONTROL_SW_MODE; - writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); - value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); - if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { - offset = 0x800; - goto detection_done; - } - - orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); - - /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ - value = orig & ~SPI_CS_CONTROL_SW_MODE; - writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); - value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); - if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { - offset = 0x800; - goto detection_done; - } + const struct lpss_config *config; + u32 value; -detection_done: - /* Now set the LPSS base */ - drv_data->lpss_base = drv_data->ioaddr + offset; + config = lpss_get_config(drv_data); + drv_data->lpss_base = drv_data->ioaddr + config->offset; /* Enable software chip select control */ value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; - __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); + __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); /* Enable multiblock DMA transfers */ if (drv_data->master_info->enable_dma) { - __lpss_ssp_write_priv(drv_data, SSP_REG, 1); + __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); - value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); + value = __lpss_ssp_read_priv(drv_data, config->reg_general); value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; - __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); + __lpss_ssp_write_priv(drv_data, config->reg_general, value); } } static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) { + const struct lpss_config *config; u32 value; - value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); + config = lpss_get_config(drv_data); + + value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); if (enable) value &= ~SPI_CS_CONTROL_CS_HIGH; else value |= SPI_CS_CONTROL_CS_HIGH; - __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); + __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); } static void cs_assert(struct driver_data *drv_data) @@ -1076,6 +1085,7 @@ static int setup(struct spi_device *spi) { struct pxa2xx_spi_chip *chip_info = NULL; struct chip_data *chip; + const struct lpss_config *config; struct driver_data *drv_data = spi_master_get_devdata(spi->master); unsigned int clk_div; uint tx_thres, tx_hi_thres, rx_thres; @@ -1085,9 +1095,10 @@ static int setup(struct spi_device *spi) tx_hi_thres = 0; rx_thres = RX_THRESH_QUARK_X1000_DFLT; } else if (is_lpss_ssp(drv_data)) { - tx_thres = LPSS_TX_LOTHRESH_DFLT; - tx_hi_thres = LPSS_TX_HITHRESH_DFLT; - rx_thres = LPSS_RX_THRESH_DFLT; + config = lpss_get_config(drv_data); + tx_thres = config->tx_threshold_lo; + tx_hi_thres = config->tx_threshold_hi; + rx_thres = config->rx_threshold; } else { tx_thres = TX_THRESH_DFLT; tx_hi_thres = 0; diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index 95a4b3bd7a5c..0485bab061fd 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -195,7 +195,7 @@ enum pxa_ssp_type { PXA910_SSP, CE4100_SSP, QUARK_X1000_SSP, - LPSS_LPT_SSP, + LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */ LPSS_BYT_SSP, };