From patchwork Mon Aug 24 03:45:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leilk Liu X-Patchwork-Id: 7060131 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 829A4C05AC for ; Mon, 24 Aug 2015 03:46:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B4751206D6 for ; Mon, 24 Aug 2015 03:46:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D479220629 for ; Mon, 24 Aug 2015 03:46:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932322AbbHXDqb (ORCPT ); Sun, 23 Aug 2015 23:46:31 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:40970 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932174AbbHXDpu (ORCPT ); Sun, 23 Aug 2015 23:45:50 -0400 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 342104642; Mon, 24 Aug 2015 11:45:48 +0800 Received: from mhfsdcap03.localdomain (10.17.3.153) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Mon, 24 Aug 2015 11:45:47 +0800 From: Leilk Liu To: Mark Brown CC: Mark Rutland , Matthias Brugger , Sascha Hauer , , , , , , Leilk Liu Subject: [PATCH v3 4/4] spi: mediatek: replace *_time name Date: Mon, 24 Aug 2015 11:45:18 +0800 Message-ID: <1440387918-22191-5-git-send-email-leilk.liu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1440387918-22191-1-git-send-email-leilk.liu@mediatek.com> References: <1440387918-22191-1-git-send-email-leilk.liu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch replaces *_time name in mtk_spi_prepare_transfer(). Signed-off-by: Leilk Liu --- drivers/spi/spi-mt65xx.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index e14f583..eaadc7e 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -238,8 +238,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) static void mtk_spi_prepare_transfer(struct spi_master *master, struct spi_transfer *xfer) { - u32 spi_clk_hz, div, high_time, low_time, holdtime, - setuptime, cs_idletime, reg_val = 0; + u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; struct mtk_spi *mdata = spi_master_get_devdata(master); spi_clk_hz = clk_get_rate(mdata->spi_clk); @@ -248,21 +247,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, else div = 1; - high_time = (div + 1) / 2; - low_time = (div + 1) / 2; - holdtime = (div + 1) / 2 * 2; - setuptime = (div + 1) / 2 * 2; - cs_idletime = (div + 1) / 2 * 2; + sck_time = (div + 1) / 2; + cs_time = sck_time * 2; - reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); - reg_val |= (((low_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); - reg_val |= (((holdtime - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); - reg_val |= (((setuptime - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); + reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); + reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); writel(reg_val, mdata->base + SPI_CFG0_REG); reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val &= ~SPI_CFG1_CS_IDLE_MASK; - reg_val |= (((cs_idletime - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); + reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); writel(reg_val, mdata->base + SPI_CFG1_REG); }