From patchwork Fri Sep 25 07:27:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Nikula X-Patchwork-Id: 7262781 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 919B0BF036 for ; Fri, 25 Sep 2015 07:27:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BE99020951 for ; Fri, 25 Sep 2015 07:27:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA4CD2095E for ; Fri, 25 Sep 2015 07:27:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752826AbbIYH1e (ORCPT ); Fri, 25 Sep 2015 03:27:34 -0400 Received: from mga09.intel.com ([134.134.136.24]:36067 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750856AbbIYH12 (ORCPT ); Fri, 25 Sep 2015 03:27:28 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 25 Sep 2015 00:27:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,585,1437462000"; d="scan'208";a="812922837" Received: from mylly.fi.intel.com (HELO mylly.fi.intel.com.) ([10.237.72.66]) by orsmga002.jf.intel.com with ESMTP; 25 Sep 2015 00:27:25 -0700 From: Jarkko Nikula To: linux-spi@vger.kernel.org Cc: Mark Brown , linux-acpi@vger.kernel.org, Daniel Mack , Haojian Zhuang , Robert Jarzmik , Jarkko Nikula Subject: [PATCH 1/2] spi: pxa2xx: Set the max_speed_hz of the master Date: Fri, 25 Sep 2015 10:27:17 +0300 Message-Id: <1443166038-31658-1-git-send-email-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.5.3 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Carry input clock of the controller in max_speed_hz of struct spi_master instead of in own driver data. They mean the same thing and more over now the max_speed_hz is not even set here. As an added bonus this allows SPI core to validate that transfer speed is not beyond the maximum input clock. This is not a problem in spi-pxa2xx as the driver doesn't use transfer speed parameter directly but via input clock divider calculation which will top at divide by one. However it's better to validate speed before passing it here. Signed-off-by: Jarkko Nikula Acked-by: Robert Jarzmik --- drivers/spi/spi-pxa2xx.c | 12 ++++++------ drivers/spi/spi-pxa2xx.h | 3 --- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 7a4cb07a5f47..36cbb0f10856 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -806,7 +806,7 @@ static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) { - unsigned long ssp_clk = drv_data->max_clk_rate; + unsigned long ssp_clk = drv_data->master->max_speed_hz; const struct ssp_device *ssp = drv_data->ssp; rate = min_t(int, ssp_clk, rate); @@ -1221,13 +1221,13 @@ static int setup(struct spi_device *spi) /* NOTE: PXA25x_SSP _could_ use external clocking ... */ cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, spi->bits_per_word); if (!pxa25x_ssp_comp(drv_data)) - dev_dbg(&spi->dev, "%ld Hz actual, %s\n", - drv_data->max_clk_rate + dev_dbg(&spi->dev, "%u Hz actual, %s\n", + drv_data->master->max_speed_hz / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), chip->enable_dma ? "DMA" : "PIO"); else - dev_dbg(&spi->dev, "%ld Hz actual, %s\n", - drv_data->max_clk_rate / 2 + dev_dbg(&spi->dev, "%u Hz actual, %s\n", + drv_data->master->max_speed_hz / 2 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), chip->enable_dma ? "DMA" : "PIO"); @@ -1477,7 +1477,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) /* Enable SOC clock */ clk_prepare_enable(ssp->clk); - drv_data->max_clk_rate = clk_get_rate(ssp->clk); + master->max_speed_hz = clk_get_rate(ssp->clk); /* Load default SSP configuration */ pxa2xx_spi_write(drv_data, SSCR0, 0); diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index b91bda26bfa8..fd7a7bc91b9f 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -46,9 +46,6 @@ struct driver_data { u32 clear_sr; u32 mask_sr; - /* Maximun clock rate */ - unsigned long max_clk_rate; - /* Message Transfer pump */ struct tasklet_struct pump_transfers;